LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 500
LPC1111FHN33/102'5
Manufacturer Part Number
LPC1111FHN33/102'5
Description
ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1111FHN33/102'5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
4000
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NXP Semiconductors
UM10398
User manual
28.6.2.7.1 Hardware and software control of interrupts
28.6.2.7 Level-sensitive and pulse interrupts
See
array, which provides the software view of the interrupt priorities.
Find the IPR number and byte offset for interrupt M as follows:
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also
described as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt
signal. Typically this happens because the ISR accesses the peripheral, causing it to clear
the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see
deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
The Cortex-M0 latches all interrupts. A peripheral interrupt becomes pending for one of
the following reasons:
A pending interrupt remains pending until one of the following:
•
•
•
•
•
•
the corresponding IPR number, N, is given by N = N DIV 4
the byte offset of the required Priority field in this register is M MOD 4, where:
– byte offset 0 refers to register bits[7:0]
– byte offset 1 refers to register bits[15:8]
– byte offset 2 refers to register bits[23:16]
– byte offset 3 refers to register bits[31:24].
the NVIC detects that the interrupt signal is active and the corresponding interrupt is
not active
the NVIC detects a rising edge on the interrupt signal
software writes to the corresponding interrupt set-pending register bit, see
Section
The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
Section 28–28.6.2.1
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
28–28.6.2.4.
Section
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
28.6.2.7.1. For a level-sensitive interrupt, if the signal is not
for more information about the access to the interrupt priority
UM10398
© NXP B.V. 2012. All rights reserved.
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