LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 256

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LPC1111FHN33/102'5

Manufacturer Part Number
LPC1111FHN33/102'5
Description
ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1111FHN33/102'5

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
4000

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LPC1111FHN33/102'5LPC1111FHN33/102
0
NXP Semiconductors
UM10398
User manual
Fig 54. Format and states in the Master Receiver mode
successful
transmission to
a Slave
transmitter
next transfer
started with a
Repeated Start
condition
Not Acknowledge
received after the
Slave address
arbitration lost in
Slave address or
Acknowledge bit
arbitration lost
and addressed
as Slave
DATA
n
08H
S
A
from Master to Slave
from Slave to Master
any number of data bytes and their associated
Acknowledge bits
this number (contained in I2STA) corresponds to a defined state of
the I
SLA
2
C bus
All information provided in this document is subject to legal disclaimers.
R
Rev. 12 — 24 September 2012
MR
40H
48H
A OR A
68H 78H B0H
A
A
A
38H
P
DATA
other Master
continues
other Master
continues
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
50H
A
to corresponding
states in Slave
DATA
mode
58H
38H
A
A
10H
P
S
other Master
continues
SLA
mode, entry
to Master
UM10398
transmit
© NXP B.V. 2012. All rights reserved.
= MT
W
R
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