LPC1111FHN33/102'5 NXP Semiconductors, LPC1111FHN33/102'5 Datasheet - Page 4

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LPC1111FHN33/102'5

Manufacturer Part Number
LPC1111FHN33/102'5
Description
ARM Microcontrollers - MCU CORTEX-M0 8 KB FL 4 KB SRAM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1111FHN33/102'5

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
4000

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0
NXP Semiconductors
UM10398
User manual
Table 1.
Series
LPC1100 series
LPC1100L series
LPC1100XL
series
LPC11C00 series LPC1100 series features plus the following additional features:
LPC11D14
(LPC1100L
series)
LPC111x/LPC11Cxx feature changes
All information provided in this document is subject to legal disclaimers.
Features overview
LPC1100 series features plus the following additional features:
LPC1100L series features plus the following new features:
LPC1100L series with LCD controller PCF8576D in a dual-chip package.
Rev. 12 — 24 September 2012
I2C, SSP, UART, GPIO
Timers and watch dog timer
10-bit ADC
Flash/SRAM memory
For a full feature list, see
Power profiles with lower power consumption in Active and Sleep modes.
Internal pull-up resistors pull up pins to full V
Programmable pseudo open-drain mode for GPIO pins.
WWDT with clock source lock capability.
Small packages (TSSOP, SO, DIP, HVQFN)
Flash page erase In-Application Programming (IAP) function.
Timer, UART, and SSP functions pinned out on additional pins.
One capture function added for each timer.
Capture-clear feature on the 16-bit and 32-bit timers for easy pulse-width
measurements.
CAN controller.
On-chip CAN drivers.
On-chip CAN transceiver (LPC11C2x).
WDT (not windowed) with clock source lock capability.
Chapter 1: LPC111x/LPC11Cxx Introductory information
Section
1.2.
DD
level.
UM10398
© NXP B.V. 2012. All rights reserved.
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