iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 24

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

Derating Logic Timing
Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num-
bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num-
bers at a particular temperature and voltage.
Maximum sysIO Buffer Performance
iCE40 Family Timing Adders
Input Adjusters
LVDS25
subLVDS
LVCMOS33
LVCMOS25
LVCMOS18
Output Adjusters
LVDS25E
subLVDSE
LVCMOS33
LVCMOS25
LVCMOS18
1. Timing adders are relative to LVCMOS25 and characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Condition table.
3. All other standards tested according to the appropriate specifications.
4. Commercial timing numbers are shown.
5. Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.
Buffer Type
Over Recommended Commercial Operating Conditions - LP Devices
LVDS25
subLVDS18
LVCMOS33
LVCMOS25
LVCMOS18
LVDS25E
subLVDS18E
LVCMOS33
LVCMOS25
LVCMOS18
1. Supported in Bank 3 only.
2. Measured with a toggling pattern
LVDS, V
subLVDS, V
LVCMOS, V
LVCMOS, V
LVCMOS, V
LVDS, Emulated, V
subLVDS, Emulated, V
LVCMOS, V
LVCMOS, V
LVCMOS, V
I/O Standard
1
1
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
CCIO
Description
Outputs
Inputs
2
3-11
CCIO
= 2.5V
Max. Speed
= 1.8V
400
400
250
250
250
250
155
250
250
155
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Timing
-0.18
-0.12
0.82
0.18
0.00
0.19
0.00
1.32
0.00
1.32
1, 2, 3, 4, 5
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS