iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 31

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

sysCLOCK PLL Timing – Preliminary
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1. Period jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock. Cycle-to-cycle jitter is taken over
2. Output clock is valid after t
3. Using LVDS25E output buffers.
4. At minimum f
5. Maximum limit to prevent PLL unlock from occurring. Does not imply the PLL will operate within the output specifications listed in this table.
6. Jitter values measured with the internal oscillator operating. The jitter values will increase with loading of the PLD fabric and in the presence
IN
OUT
VCO
PFD
DT
PH
OPJIT
LOCK
UNLOCK
IPJIT
HI
LO
FDTAP
STABLE
STABLE_PW
RST
RSTREC
DYNAMIC-SETUP
DYNAMIC-HOLD
DYNAMIC_WD
1000 cycles. Phase jitter is taken over 2000 cycles. All values per JESD65B.
of SSO noise.
Parameter
5
2, 4
1, 6
4
4
PFD
. As the f
Input Clock Frequency
(REFERENCECLK, EXTFEEDBACK)
Output Clock Frequency (PLLOUT)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Output Clock Cycle-to-cycle Jitter
Output Clock Phase Jitter
PLL Lock-in Time
PLL Unlock Time
Input Clock Period Jitter
Input Clock High Time
Input Clock Low Time
Fine Delay adjustment, per Tap
LATCHINPUTVALUE LOW to PLL Stable
LATCHINPUTVALUE Pulse Width
RESET Pulse Width
RESET Recovery Time
DYNAMICDELAY Setup Time
DYNAMICDELAY HOLD Time
DYNAMICDELAY Pulse Width
PFD
LOCK
increases the time will decrease to approximately 60% the value listed.
for PLL reset and dynamic delay adjustment.
Descriptions
Over Recommended Operating Conditions
3
3-18
f
f
f
f
f
f
f
f
90% to 90%
10% to 10%
OUT
OUT
OUT
OUT
PFD
PFD
PFD
PFD
<= 100 MHz
> 100 MHz
 20 MHz
< 20 MHz
<= 100 MHz
> 100 MHz
<= 100 MHz
> 100 MHz
Conditions
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Min.
10
16
10
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
133
275
133
—
—
—
—
—
—
—
Cycles
ps p-p
Units
UIPP
UIPP
UIPP
UIPP
UIPP
UIPP
UIPP
VCO
MHz
MHz
MHz
MHz
ms
ms
ms
us
ns
ns
ns
ns
ns
ns
ns
%
%