iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 35

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

April 2013
Signal Descriptions
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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General Purpose
PIOx
DP[Pair Number][A/B]
NC
GND
VCC
VCCIO_x
PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)
VCCPLLx
GNDPLLx
GBINx
Programming and Configuration
CBSEL[0:1]
CRESET_B
CDONE
VCC_SPI
SPI_SCK
SPI_SS_B
SPI_SI
SPI_SO
Signal Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
I
iCE40 LP/HX Family Data Sheet
User IO pin. x determines the Banks 0-3.
Differential I/O pair. Only available in I/O Bank 3. ‘A’ = negative input. 
‘B’ = positive input.
No connect
GND – Ground. Dedicated pins. It is recommended that all GNDs are
tied together.
VCC – The power supply pins for core logic. Dedicated pins. It is recom-
mended that all VCCs are tied to the same supply.
VCCIO – The power supply pins for I/O Bank x. Dedicated pins. All
VCCIOs located in the same bank are tied to the same supply.
PLL VCC – Power. Dedicated pins. The PLL requires a separate power
and ground that is quiet and stable to reduce the output clock jitter of the
PLL.
PLL GND – Ground. Dedicated pins. The sysCLOCK PLL has the DC
ground connection made on the FPGA, so the external PLL ground con-
nection (GNDPLL) must NOT be connected to the board’s ground.
Global pads. Two per side.
Dual function pins. I/Os when not used as CBSEL. Optional ColdBoot
configuration SELect input, if ColdBoot mode is enabled.
Configuration Reset, active Low. Dedicated input. No internal pull-up
resistor. Either actively drive externally or connect a 10 KOhm pull-up
resistor to VCCIO_2.
Configuration Done. Includes a permanent weak pull-up resistor to
VCCIO_2. If driving external devices with CDONE output, connect a 10
KOhm pull-up resistor to VCCIO_2.
SPI interface voltage supply input. Must have a valid voltage even if con-
figuring from NVCM.
Input Configuration Clock for configuring an FPGA in Slave SPI mode.
Output Configuration Clock for configuring an FPGA configuration
modes.
SPI Slave Select. Active Low. Includes an internal weak pull-up resistor
to VCC_SPI during configuration. During configuration, the logic level
sampled on this pin determines the configuration mode used by the
iCE40 device. An input when sampled at the start of configuration. An
input when in SPI Peripheral configuration mode (SPI_SS_B = Low). An
output when in Master SPI Flash configuration mode.
Slave SPI serial data input and master SPI serial data output
Slave SPI serial data output and master SPI serial data input
4-1
Pinout Information
Descriptions
DS1040
Pinout Information_01.1
Data Sheet DS1040