iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 33

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

sysCONFIG Port Timing Specifications
Table 3-3. Available Oscillator Frequencies
f
f
f
Master SPI
f
t
1. iCE40LP4K/iCE40LP8K, iCE40HX1K/iCE40HX4K/iCE40HX8K status is Preliminary.
2. Does not apply for NVCM.
MCLK
MCLK
OSCD
OSCL
OSCH
Symbol
Symbol
Oscillator Mode
Default
Low Frequency
High Frequency
Off
MCLK clock frequency
CRESET_B high to first MCLK edge
Frequency (MHz)
Parameter
Min.
16
27
4
0
Max.
11
32
53
0
Default oscillator frequency. Slow enough to safely operate with most SPI
serial PROM.
Supported by most SPI serial Flash PROMs.
Supported by some high-speed SPI serial Flash PROMs.
Oscillator turned off by default after configuration to save power.
3-20
Default Frequency
Default Frequency
Default Frequency
Default Frequency
Default Frequency
iCE40LP/HX1K -
iCE40LP/HX1K -
iCE40LP/HX1K -
iCE40LP/HX4K -
iCE40LP/HX4K -
iCE40LP/HX4K -
iCE40LP/HX8K -
iCE40LP/HX8K -
iCE40LP/HX8K -
High Frequency
High Frequency
High Frequency
High Frequency
High Frequency
Low Frequency
Low Frequency
Low Frequency
Low Frequency
Low Frequency
1
iCE40LP384 -
iCE40LP384 -
iCE40LP384 -
Conditions
(Continued)
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
Description
1200
1200
1200
1200
1200
1200
Min.
800
800
800
16
27
4
Max.
11
32
53
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
us
us
us
us
us
us
us
us
us
us
us
us