iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 7

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

Global Reset Control
The global reset control signal connects to all PLB and PIO flip-flops on the iCE40 device. The global reset signal is
automatically asserted throughout the configuration process, forcing all flip-flops to their defined wake-up state. For
PLB flip-flops, the wake-up state is always reset, regardless of the PLB flip-flop primitive used in the application.
sysCLOCK Phase Locked Loops (PLLs)
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The iCE40 devices have one or more sys-
CLOCK PLLs. REFERENCECLK is the reference frequency input to the PLL and its source can come from an
external I/O pin or from internal routing. EXTFEEDBACK is the feedback signal to the PLL which can come from
internal routing or an external I/O pin. The feedback divider is used to multiply the reference frequency and thus
synthesize a higher frequency clock output.
The PLLOUT output has an output divider, thus allowing the PLL to generate different frequencies for each output.
The output divider can have a value from 1 to 6. The PLLOUT outputs can all be used to drive the iCE40 global
clock network directly or general purpose routing resources can be used.
The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected. A block diagram of the PLL is shown in Figure 2-3.
The timing of the device registers can be optimized by programming a phase shift into the PLLOUT output clock
which will advance or delay the output clock with reference to the REFERENCECLK clock. This phase shift can be
either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock
after a phase adjustment on the output used as the feedback source and not relock until the t
been satisfied.
For more details on the PLL, see TN1251,
Figure 2-3. PLL Diagram
Table 2-3 provides signal descriptions of the PLL block.
DYNAMICDELAY[7:0]
LATCHINPUTVALUE
REFERENCECLK
EXTFEEDBACK
BYPASS
RESET
Low Power mode
(iCEgate enabled)
Divider
DIVR
Input
Detector
Phase
Feedback_Path
Feedback
Divider
DIVF
BYPASS
Low-Pass
RANGE
Filter
iCE40 sysCLOCK PLL Design and Usage
GNDPLL
Controlled
Oscillator
Voltage
(VCO)
Adjustment
Fine Delay
Feedback
2-4
VCCPLL
EXTERNAL
SIMPLE
Divider
DIVQ
VCO
Phase
Shifter
iCE40 LP/HX Family Data Sheet
Guide.
Adjustment
Output Port
Fine Delay
LOCK
Architecture
parameter has
PLLOUTCORE
PLLOUTGLOBAL
LOCK