iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 28

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

iCE40 External Switching Characteristics – Preliminary – HX Devices
Clocks
Primary Clocks
f
t
t
Pin-LUT-Pin Propagation Delay
t
General I/O Pin Parameters (Using Global Buffer Clock without PLL)
t
t
t
t
General I/O Pin Parameters (Using Global Buffer Clock with PLL)
t
t
t
MAX_GBUF
W_GBUF
SKEW_GBUF
PD
SKEW_IO
CO
SU
H
COPLL
SUPLL
HPLL
Parameter
Frequency for Global Buffer Clock network All iCE40HX devices
Clock Pulse Width for Global Buffer
Global Buffer Clock Skew Within a Device
Best case propagation delay through one
LUT-4
Data bus skew across a bank of IOs
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
Over Recommended Operating Conditions
Description
3-15
All iCE40HX devices
iCE40HX1K
iCE40HX4K
iCE40HX8K
All iCE40HX devices
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
iCE40HX1K
iCE40HX4K
iCE40HX8K
Device
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
-0.43
-0.43
Min.
2.38
2.38
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
7.30
5.41
5.41
300
300
290
290
—
—
—
—
—
—
—
—
—
—
—
—
—
1, 2, 3
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns