iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 32

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

SPI Master or NVCM Configuration Time
sysCONFIG Port Timing Specifications
All Configuration Modes
f
t
t
t
t
t
1. Assumes sysMEM Block is initialized to an all zero pattern if they are used.
2. The NVCM download time is measured with a fast ramp rate starting from the maximum voltage of POR trip point.
3. iCE40LP4K/iCE40LP8K, iCE40HX1K/iCE40HX4K/iCE40HX8K status is Preliminary.
t
t
Slave SPI
t
MAX
CCLKH
CCLKL
STSU
STH
STCO
CRESET_B
DONE_IO
CR_SCK
Symbol
2
Symbol
t
CONFIG
Minimum CRESET_B
Low pulse width
required to restart con-
figuration, from falling
edge to rising edge
Number of configura-
tion clock cycles after
CDONE goes High
before the PIO pins are
activated
Minimum time from a
rising edge on
CRESET_B until the
first SPI write opera-
tion, first SPI_SCK. Dur-
ing this time, the iCE40
device is clearing its
internal configuration
memory
CCLK clock frequency
CCLK clock pulse width
high
CCLK clock pulse width
low
CCLK setup time
CCLK hold time
CCLK falling edge to
valid output
POR/CRESET_B to
Parameter
Device I/O Active
Parameter
iCE40LP384 - Default
iCE40LP384 - Low frequency
iCE40LP384 - High frequency
iCE40LP/HX1K - Default
iCE40LP/HX1K - Low frequency
iCE40LP/HX1K - High frequency
iCE40LP/HX4K - Default
iCE40LP/HX4K - Low frequency
iCE40LP/HX4K - High frequency
iCE40LP/HX8K - Default
iCE40LP/HX8K - Low frequency
iCE40LP/HX8K - High frequency
iCE40LP/HX1K
iCE40LP/HX4K
iCE40LP/HX8K
iCE40LP384
Conditions
Read
Write
3-19
Conditions
1
1, 2, 3
DC and Switching Characteristics
iCE40 LP/HX Family Data Sheet
1200
1200
Min.
200
800
12
12
49
20
20
13
0
5
Typ.
230
110
230
110
53
25
13
70
70
Max.
__
25
25
—
—
—
—
—
—
—
—
—
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Clock Cycles
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
Units
MHz
MHz
ns
us
us
ns
ns
ns
ns
ns