iCE40LP1K-CM49TR Lattice, iCE40LP1K-CM49TR Datasheet - Page 6

• Manufacturer Part Number: iCE40LP1K-CM49TR
• Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs, 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE40LP1K-CM49TR

• Rohs: yes

Routing
There are many resources provided in the iCE40 devices to route signals individually with related control signals.
The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PLB connections are made with three different types of routing resources: Adjacent (spans two PLBs), x4
(spans five PLBs) and x12 (spans thirteen PLBs). The Adjacent, x4 and x12 connections provide fast and efficient
connections in the diagonal, horizontal and vertical directions.
The design tool takes the output of the synthesis tool and places and routes the design.
Clock/Control Distribution Network
Each iCE40 device has eight global inputs, two pins on each side of the device. Note that not all GBINs are avail-
able in all packages.
These global inputs can be used as high fanout nets, clock, reset or enable signals. The dedicated global pins are
identified as GBIN[7:0] and the global buffers are identified as-GBUF[7:0]. These eight inputs may be used as gen-
eral purpose I/O if they are not used to drive the clock nets. Global buffer GBUF7 in I/O Bank 3 also provides an
optional direct LVDS25 or subLVDS differential clock input.
Table 2-2 lists the connections between a specific global buffer and the inputs on a PLB. All global buffers optionally
connect to the PLB CLK input. Any four of the eight global buffers can drive logic inputs to a PLB. Even-numbered
global buffers optionally drive the Set/Reset input to a PLB. Similarly, odd-numbered buffers optionally drive the
PLB clock-enable input.
Table 2-2. Global Buffer (GBUF) Connections to Programmable Logic Blocks
The maximum frequency for the global buffers are shown in the iCE40 External Switching Characteristics tables
later in this document.
Global Hi-Z Control
The global high-impedance control signal, GHIZ, connects to all I/O pins on the iCE40 device. This GHIZ signal is
automatically asserted throughout the configuration process, forcing all user I/O pins into their high-impedance
state.
Global Buffer
GBUF0
GBUF1
GBUF2
GBUF3
GBUF4
GBUF5
GBUF6
GBUF7
Yes, any 4 of 8
GBUF Inputs
LUT Inputs
Clock
2-3
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Clock Enable
iCE40 LP/HX Family Data Sheet
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Architecture
Reset
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