1893CKLFT IDT, 1893CKLFT Datasheet - Page 11

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

4.1.2 Specific Reset Operations
4.1.2.1 Hardware Reset
4.1.2.2 Power-On Reset
ICS1893CK-40, Rev. C, 06/02/09
This section discusses the following specific ways that the ICS1893CK-40 can be reset:
•
•
•
Note:
Entering Hardware Reset
Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware
reset (that is, the ICS1893CK-40 enters the reset state). During reset, the ICS1893CK-40 executes the
steps listed in
Exiting Hardware Reset
After the signal on the RESETn pin transitions from a low to a high state, the ICS1893CK-40 completes in
640 ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in
first five steps are completed, the Serial Management Port is ready for normal operations, but this action
does not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and
receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details
on this transition, see
Note:
1. The MAC Interface is not available for use until the TXCLK and RXCLK are valid.
2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit
Entering Power-On Reset
When power is applied to the ICS1893CK-40, it waits until the potential between VDD and VSS achieves a
minimum voltage before entering reset and executing the steps listed in
After entering reset from a power-on condition, the ICS1893CK-40 remains in reset for approximately 20
µs. (For details on this transition, see
Exiting Power-On Reset
The ICS1893CK-40 automatically exits reset and performs the same steps as for a hardware reset. (See
Section 4.1.1.2, “Exiting
Note:
Hardware reset (using the RESETn pin)
Power-on reset (applying power to the ICS1893CK-40)
Software reset (using Control Register bit 0.15)
that is used to initiate a software reset.
At the completion of a reset (either hardware, power-on, or software), the ICS1893CK-40 sets all
registers to their default values.
The only difference between a hardware reset and a power-on reset is that during a power-on
reset, the ICS1893CK-40 isolates its RESETn input pin. All other functionality is the same. As with
a hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset.
ICS1893CK-40 Data Sheet Rev. C - Release
Section 4.1.1.1, “Entering
Section 9.5.16, “Reset: Hardware Reset and
Reset”.)
Copyright © 2009, Integrated Device Technology, Inc.
Section 9.5.15, “Reset: Power-On
Reset”.
All rights reserved.
11
Section 4.1.1.2, “Exiting
Power-Down”.]
Chapter 4 Operating Modes Overview
Section 4.1.1.1, “Entering
Reset”.)
Reset”. After the
June 2009
Reset”.