1893CKLFT IDT, 1893CKLFT Datasheet - Page 92

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

ICS1893CK-40, Rev. C, 06/02/09
Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued)
RXCLK
RXD0
RXD1
RXD2
RXD3
RXDV
Name
Pin
ICS1893CK-40 Data Sheet - Release
Number
Pin
23
21
20
19
18
22
Output
Output
Output
Type
Pin
Copyright © 2009, Integrated Device Technology, Inc.
Receive Clock.
The ICS1893CK-40 sources the RXCLK to the MAC interface. The
ICS1893CK-40 uses RXCLK to synchronize the signals on the following
pins: RXD[3:0], RXDV, and RXER. The following table contrasts the
behavior on the RXCLK pin when the mode for the ICS1893CK-40 is
either 10Base-T or 100Base-TX.
Receive Data 0–3.
Receive Data Valid.
The ICS1893CK-40 asserts RXDV to indicate to the MAC that data is
available on the MII Receive Bus (RXD[3:0]). The ICS1893CK-40:
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
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•
•
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RXD0 is the least-significant bit and RXD3 is the most-significant bit of
the MII receive data nibble.
While the ICS1893CK-40 asserts RXDV, the ICS1893CK-40 transfers
the receive data signals on the RXD0–RXD3 pins to the MAC Interface
synchronously on the rising edges of RXCLK.
Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see
“100M/MII Media Independent Interface: Synchronous Receive
Timing”.)
De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
The RXCLK frequency is 2.5
MHz.
The ICS1893CK-40 generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893CK-40 switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893CK-40 is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
The RXCLK aligns once per
packet.
All rights reserved.
10Base-T
92
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
The RXCLK frequency is 25 MHz.
The ICS1893CK-40 generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the
ICS1893CK-40 uses the REF_IN
clock to generate the RXCLK.
While the ICS1893CK-40 is
bringing up a link, a clock phase
change of up to 360 degrees can
occur.
The RXCLK aligns once, when
the link is being established.
100Base-TX
Chapter 9.5.6,
June 2009