1893CKLFT IDT, 1893CKLFT Datasheet - Page 31

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

6.3.4.2 PMA Receive Modules
6.3.5 PCS Control Signal Generation
ICS1893CK-40, Rev. C, 06/02/09
Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to
the MAC Interface. Detection of an error forces the Receive state machine to assert the receive error signal
(RX_ER) and wait for the next symbol. If the ICS1893CK-40 Receive state machine detects a premature
end, it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic one, and
transitions to the IDLE State.
The ICS1893CK-40 has a PMA Receive module that provides the following functions:
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•
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For the PCS sublayer, there are two control signals: a Carrier Sense signal (CRS) and a Collision Detect
signal (COL).
The CRS control signals is generated as follows:
1. When a logic zero is detected in an idle bit stream, the Receive Functions examines the ensuing bits.
2. When the Receive Functions find the first two non-contiguous zero bits, the Receive state machine
3. As a result, the Boolean Receiving variable is set to TRUE.
4. Consequently, the Carrier Sense state machine moves into the Carrier Sense ‘on’ state, which asserts
5. If the PCS Functions:
The COL control signal is generated by the transmit modules. For details, see
Transmit
NRZI Decoding
The Receive module performs the NRZI decoding on the serial bit stream received from the Twisted-Pair
Physical Medium Dependent (TP-PMD) sublayer. It converts the bit stream to a unipolar, positive, binary
format that the PMA subsequently passes to the PCS.
Receive Clock Recovery
The Receive Clock Recovery function consists of a phase-locked loop (PLL) that operates on the serial
data stream received from the PMD sublayer. This PLL automatically synchronizes itself to the clock
encoded in the serial data stream and then provides both a recovered clock and data stream to the PCS.
Link Monitoring
– The ICS1893CK-40’s PMA Link Monitoring function observes the Receive Clock PLL. If the Receive
– In addition, the ICS1893CK-40’s PMA Link Monitor function continually audits the state of the
moves into the Carrier Detect state.
the CRS signal.
a. Cannot confirm either the /I/J/ (IDLE, J) symbols or the /J/K/ symbols, the receive error signal
b. Can confirm the /I/J/K/ symbols, then the Receive state machine transitions to the ‘Receive’ state.
Clock PLL cannot acquire ‘lock’ on the serial data stream, it asserts an error signal. The status of this
error signal can be read in the QuickPoll Detailed Status Register’s PLL Lock Error bit (bit 17.9). This
bit is a latching high (LH) bit. (For more information on latching high and latching low bits, see
7.1.4.1, “Latching High Bits”
connection with the remote link partner. It asserts a receive channel error if a receive signal is not
detected or if a PLL Lock Error occurs. These errors, in turn, generate a link fault and force the link
monitor function to clear both the Status Register’s Link Status bit (bit 1.2) and the QuickPoll Detailed
Status Register’s Link Status bit (bit 17.0).
(RX_ER) is asserted, and the Receive state machine returns to the IDLE state. In IDLE, the
Boolean Receiving variable is set to FALSE, thereby causing the Carrier Sense state machine to
set the CRS signal to FALSE.
ICS1893CK-40 Data Sheet Rev. C - Release
Module”.
Copyright © 2009, Integrated Device Technology, Inc.
and
Section 7.1.4.2, “Latching Low
All rights reserved.
31
Bits”.)
Section 6.3.3.1, “PCS
Chapter 6 Functional Blocks
June 2009
Section