1893CKLFT IDT, 1893CKLFT Datasheet - Page 49

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

7.2.8 Duplex Mode (bit 0.8)
7.2.9 Collision Test (bit 0.7)
7.2.10 IEEE Reserved Bits (bits 0.6:0)
ICS1893CK-40, Rev. C, 06/02/09
This bit provides a means of controlling the ICS1893CK-40 Duplex Mode.
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This bit controls the ICS1893CK-40 Collision Test function. When an STA sets bit 0.7 to logic:
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The IEEE reserves these bits for future use. When an STA:
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The ICS1893CK-40 uses some reserved bits to invoke auxiliary functions. To ensure proper operation of
the ICS1893CK-40, an STA must maintain the default value of these bits. Therefore, ICS recommends that
during any STA write operation, an STA write the default value to all reserved bits, even those bits that are
Read Only.
The function of bit 0.8 depends on the Auto-Negotiation Enable bit, 0.12. When the auto-negotiation
process is:
Zero, the ICS1893CK-40 disables the collision detection circuitry for the Collision Test function. In this
case, the COL signal does not track the TXEN signal. (The default value for this bit is logic zero, that is,
disabled.)
One, as per the ISO/IEE 8802-3 standard, clause 22.2.4.1.9, the ICS1893CK-40 enables the collision
detection circuitry for the Collision Test function, even if the ICS1893CK-40 is in Loopback mode (that is,
bit 0.14 is set to 1). In this case, the Collision Test function tracks the Collision Detect signal (COL) in
response to the TXEN signal. The ICS1893CK-40 asserts the Collision signal (COL) within 512 bit times
of receiving an asserted TXEN signal, and it de-asserts COL within 4 bit times of the de-assertion of the
TXEN signal.
Reads a reserved bit, the ICS1893CK-40 returns a logic zero.
Writes to a reserved bit, it must use the default value specified in this data sheet.
– Enabled, the ICS1893CK-40 isolates bit 0.8 and relies upon the results of the auto-negotiation
– Disabled, bit 0.8 determines the Duplex mode. Setting bit 0.8 to logic:
process to establish the duplex mode.
• Zero selects half-duplex operations.
• One selects full-duplex operations. (When the ICS1893CK-40 is operating in Loopback mode, it
isolates bit 0.8, which has no effect on the operation of the ICS1893CK-40.)
ICS1893CK-40 Data Sheet Rev. C - Release
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
49
Chapter 7 Management Register Set
June 2009