1893CKLFT IDT, 1893CKLFT Datasheet - Page 25

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

6.1 Functional Block: Media Independent Interface
ICS1893CK-40, Rev. C, 06/02/09
All ICS1893CK-40 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition,
the ICS1893CK-40 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5
MHz (for 10Base-T operations).
The Media Independent Interface (MII) consists of two primary components:
1. An interface between a MAC (Media Access Control sublayer) and the PHY (that is, the
2. An interface between the PHY (the ICS1893CK-40) and an STA (Station Management entity). The
The ICS1893CK-40 Management Register set (discussed in
consists of the following:
•
•
•
Basic Management registers.
As defined in the ISO/IEC 8802-3 standard, these registers include the following:
Extended Management registers.
As defined in the ISO/IEC 8802-3 standard, the ICS1893CK-40 supports Extended registers that provide
access to the Organizationally Unique Identifier and all auto-negotiation functionality.
ICS (Vendor-Specific) Management registers.
The ICS1893CK-40 provides vendor-specific registers for enhanced PHY operations. Among these is
the QuickPoll Detailed Status Register that provides a comprehensive and consolidated set of real-time
PHY information. Reading the QuickPoll register enables the MAC to obtain comprehensive status data
with a single register access.
– Control Register (register 0), which handles basic device configuration
– Status Register (register 1), which reports basic device capabilities and status
ICS1893CK-40). This MAC-PHY part of the MII consists of three subcomponents:
a. A synchronous Transmit interface that includes the following signals:
b. A synchronous Receive interface that includes the followings signals:
STA-PHY part of the MII is a two-wire, Serial Management Interface that consists of the following:
a. A clock (MDC)
b. A synchronous, bi-directional data signal (MDIO) that provides an STA with access to the
ICS1893CK-40 Management Register set
ICS1893CK-40 Data Sheet Rev. C - Release
(1) A data nibble, TXD[3:0]
(2) A delimiter, TXEN
(3) A clock, TXCLK
(1) A data nibble, RXD[3:0]
(2) An error indicator, RXER
(3) A delimiter, RXDV
(4) A clock, RXCLK
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
25
Chapter 7, “Management Register
Chapter 6 Functional Blocks
Set”)
June 2009