1893CKLFT IDT, 1893CKLFT Datasheet - Page 48

• Manufacturer Part Number: 1893CKLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CKLFT

• Rohs: yes
• Part # Aliases: ICS1893CKLFT

7.2.5 Low Power Mode (bit 0.11)
7.2.6 Isolate (bit 0.10)
7.2.7 Restart Auto-Negotiation (bit 0.9)
ICS1893CK-40, Rev. C, 06/02/09
This bit provides one way to control the ICS1893CK-40 low-power mode function. When bit 0.11 is logic:
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Note:
This bit controls the ICS1893CK-40 Isolate function. When bit 0.10 is logic:
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The default value for bit 0.10 depends upon the PHY address of
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This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
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Zero, there is no impact to ICS1893CK-40 operations.
One, the ICS1893CK-40 enters the low-power mode. In this case, the ICS1893CK-40 disables all
internal functions and drives all MAC output pins low except for those that support the MII Serial
Management Port. In addition, the ICS1893CK-40 internally activates the TPTRI function to tri-state the
signals on the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Zero, there is no impact to ICS1893CK-40 operations.
One, the ICS1893CK-40 electrically isolates its data paths from the MAC Interface. The ICS1893CK-40
places all MAC output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0]) in a high-impedance state and
it isolates all MAC input signals (TXD[3:0], TXEN, and TXER). In this mode, the Serial Management
Interface continues to operate normally (that is, bit 0.10 does not affect the Management Interface).
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893CK-40 isolates itself
from the MAC Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893CK-40 does not
isolate its MAC Interface.
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893CK-40 isolates any attempt by the STA
to set bit 0.9 to logic one.
One (as set by an STA), the ICS1893CK-40 restarts the auto-negotiation process. Once the
auto-negotiation process begins, the ICS1893CK-40 automatically sets this bit to logic zero, thereby
providing the self-clearing feature.
There are two ways the ICS1893CK-40 can enter low-power mode. When entering low-power
mode:
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ICS1893CK-40 Data Sheet - Release
By setting bit 0.11 to logic one, the ICS1893CK-40 maintains the value of all Management
Register bits except the latching high (LH) and latching low (LL) status bits, which are
re-initialized to their default values instead. (For more information on latching high and latching
low bits, see
During a reset, the ICS1893CK-40 sets all management register bits to their default values.
Section 7.1.4.1, “Latching High Bits”
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
48
and
Section 7.1.4.2, “Latching Low
Table
7-16. If the PHY address:
Chapter 7 Management Register Set
Bits”.)
June 2009