C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet - Page 190
C8051F707-GMR
Manufacturer Part Number
C8051F707-GMR
Description
8-bit Microcontrollers - MCU 16kB Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F707-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F70x/71x
SFR Definition 28.1. XBR0: Port I/O Crossbar Register 0
SFR Address = 0xE1; SFR Page = F
190
Name
Reset
7:6
Bit
Type
5
4
3
2
1
0
Bit
SYSCKE SYSCLK Output Enable.
Unused
SMB0E
CP0AE
URT0E
SPI0E
Name
CP0E
R
7
0
Read = 00b; Write = Don’t Care.
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
0: SYSCLK unavailable at Port pin.
1: SYSCLK output routed to Port pin.
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
R
6
0
CP0AE
R/W
5
0
CP0E
R/W
Rev. 1.0
4
0
Function
SYSCKE
R/W
3
0
SMB0E
R/W
2
0
SPI0E
R/W
1
0
URT0E
R/W
0
0
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