C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet - Page 230
C8051F707-GMR
Manufacturer Part Number
C8051F707-GMR
Description
8-bit Microcontrollers - MCU 16kB Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F707-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F70x/71x
SFR Definition 30.4. SMB0ADM: SMBus Slave Address Mask
SFR Address = 0xBB; SFR Page = F
230
Name
Reset
7:1
Bit
Type
0
Bit
SLVM[6:0]
EHACK
Name
7
1
SMBus Slave Address Mask.
Defines which bits of register SMB0ADR are compared with an incoming address
byte, and which bits are ignored. Any bit set to 1 in SLVM[6:0] enables compari-
sons with the corresponding bit in SLV[6:0]. Bits set to 0 are ignored (can be either
0 or 1 in the incoming address).
Hardware Acknowledge Enable.
Enables hardware acknowledgement of slave address and received data bytes.
0: Firmware must manually acknowledge all incoming address and data bytes.
1: Automatic Slave Address Recognition and Hardware Acknowledge is Enabled.
6
1
5
1
SLVM[6:0]
R/W
Rev. 1.0
4
1
Function
3
1
2
1
1
1
EHACK
R/W
0
0
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