C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet - Page 200
C8051F707-GMR
Manufacturer Part Number
C8051F707-GMR
Description
8-bit Microcontrollers - MCU 16kB Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F707-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F70x/71x
SFR Definition 28.17. P2: Port 2
SFR Address = 0xA0; SFR Page = All Pages; Bit Addressable
SFR Definition 28.18. P2MDIN: Port 2 Input Mode
SFR Address = 0xF3; SFR Page = F
200
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
P2MDIN[7:0]
P2[7:0]
Name
Name
7
1
7
1
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Analog Configuration Bits for P2.7–P2.0 (respectively).
Port pins configured for analog mode have their weak pullup, digital driver, and
digital receiver disabled.
0: Corresponding P2.n pin is configured for analog mode.
1: Corresponding P2.n pin is not configured for analog mode.
6
1
6
1
Description
5
1
5
1
Rev. 1.0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
1
4
1
P2MDIN[7:0]
P2[7:0]
R/W
R/W
Function
Write
3
1
3
1
2
1
2
1
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
1
1
1
1
Read
0
1
0
1
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