C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet - Page 38
C8051F707-GMR
Manufacturer Part Number
C8051F707-GMR
Description
8-bit Microcontrollers - MCU 16kB Cap Sense
Manufacturer
Silicon Labs
Datasheet
1.C8051F709-GQR.pdf
(306 pages)
Specifications of C8051F707-GMR
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
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C8051F70x/71x
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Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
pad is to be 60 m minimum, all the way around the pad.
solder paste release.
Components.
Dimension
C1
C2
E
X
Y
Table 4.2. TQFP-64 PCB Land Pattern Dimensions
Figure 4.2. TQFP-64 PCB Land Pattern
Rev. 1.0
11.30
11.30
0.20
1.40
Min
0.50 BSC
11.40
11.40
Max
0.30
1.50
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