C8051F707-GMR Silicon Labs, C8051F707-GMR Datasheet - Page 93

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C8051F707-GMR

Manufacturer Part Number
C8051F707-GMR
Description
8-bit Microcontrollers - MCU 16kB Cap Sense
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F707-GMR

Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
SFR Definition 15.9. CS0PM: Capacitive Sense Pin Monitor
SFR Address = 0x9F; SFR Page = F
Name
Reset
Bit
1:0
Type
7
6
5
4
3
2
Bit
CSPMMD[1:0] CS0 Pin Monitor Mode.
SMBPM
PCAPM
CP0PM
PIOPM
UAPM
SPIPM
UAPM
Name
R/W
7
0
SPIPM
UART Pin Monitor Enable.
Enables monitoring of the UART TX pin.
SPI Pin Monitor Enable.
Enables monitoring SPI output pins.
SMBus Pin Monitor Enable.
Enables monitoring of the SMBus pins.
PCA Pin Monitor Enable.
Enables monitoring of PCA output pins.
Port I/O Pin Monitor Enable.
Enables monitoring of writes to the port latch registers.
CP0 Pin Monitor Enable.
Enables monitoring of the comparator CP0 (synchronous) output.
Selects the operation to take when a monitored signal changes state.
00: Always retry bit cycles on a pin state change.
01: Retry up to twice on consecutive bit cycles.
10: Retry up to four times on consecutive bit cycles.
11: Reserved.
R/W
6
0
SMBPM
R/W
5
0
PCAPM
R/W
Rev. 1.0
4
0
Description
PIOPM
R/W
3
0
CP0PM
R/W
C8051F70x/71x
2
0
CSPMMD[1:0]
1
0
R/W
0
0
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