DS2155LC1 Maxim Integrated, DS2155LC1 Datasheet - Page 116
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DS2155LC1
Manufacturer Part Number
DS2155LC1
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS2155GNB.pdf
(238 pages)
- Current page: 116 of 238
- Download datasheet (2Mb)
22.3 Method 3: Internal Register Scheme Based on CRC4 Multiframe
The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC4
multiframe bit in Status Register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these
registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first
received. See the following register descriptions for more details.
The transmit side also contains a set of eight registers (TSiAF, TSiNAF, TRA, and TSa4–TSa8) that,
through the transmit Sa bit control register (TSaCR), can be programmed to insert Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in Status Register 2 (SR4.4).
The host can use the SR4.4 bit to know when to update these registers. It has 2ms to update the data or
else the old data is retransmitted. The MSB of each register is the first bit transmitted. See the following
register descriptions for more details.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Si Bit of Frame 14 (SiF14)
Bit 1/Si Bit of Frame 12 (SiF12)
Bit 2/Si Bit of Frame 10 (SiF10)
Bit 3/Si Bit of Frame 8 (SiF8)
Bit 4/Si Bit of Frame 6 (SiF6)
Bit 5/Si Bit of Frame 4 (SiF4)
Bit 6/Si Bit of Frame 2 (SiF2)
Bit 7/Si Bit of Frame 0 (SiF0)
SiF0
7
0
SiF2
RSiAF
Received Si Bits of the Align Frame
C8h
6
0
SiF4
5
0
SiF6
4
0
116 of 238
SiF8
3
0
SiF10
2
0
SiF12
1
0
SiF14
0
0
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