DS2155LC1 Maxim Integrated, DS2155LC1 Datasheet - Page 212

• Manufacturer Part Number: DS2155LC1
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store
Enabled)
Note 1: TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG is ignored during channel 24).
Figure 35-10. Transmit-Side 2.048MHz Boundary Timing (Elastic Store
Enabled)
Note 1: TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.
Note 2: TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).
Note 3: TCHBLK is forced to 1 in the same channels as TSER is ignored (see Note 1).
Note 4: The F-bit position for the T1 frame is sampled and passed through the transmit-side elastic store into the MSB bit position of channel 1.
TCHBLK
(Normally, the transmit-side formatter overwrites the F-bit position unless the formatter is programmed to pass through the F-bit
position.)
TSYSCLK
TSYSCLK
TCHBLK
TCHCLK
TSSYNC
TCHCLK
TSSYNC
TSER
TSER
TSIG
TSIG
2,3
1
1
CHANNEL 23
CHANNEL 31
CHANNEL 31
CHANNEL 23
A
A
B
B
C/A D/B
C/A D/B
LSB MSB
LSB MSB
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CHANNEL 24
CHANNEL 24
CHANNEL 32
CHANNEL 32
A
A
B
B
C/A D/B
C/A D/B
LSB
LSB
F
F MSB
4
CHANNEL 1
CHANNEL 1
CHANNEL 1
CHANNEL 1
A
A