XRT83SL28ES Exar, XRT83SL28ES Datasheet
XRT83SL28ES
Specifications of XRT83SL28ES
Related parts for XRT83SL28ES
XRT83SL28ES Summary of contents
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... XRT83SL28 operates from a single 3.3V power supply. The LIU features are programmed through a standard serial microprocessor interface or hardware control. EXAR’s LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT IGURE ARDWARE ODE LOCK Channels TCLK HDB3 TPOS Encoder TNEG/CODE Remote Loopback RCLK HDB3 RPOS Decoder RNEG/LCV RLOS Test ICT D XRT83SL28 IAGRAM OF THE ...
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REV. 1.0.0 FEATURES • Fully integrated 8-Channel short haul transceivers for E1 (2.048MHz) applications. • Internal Impedance matching on both receive and transmit for 75Ω (E1) or 120Ω (E1) applications. • Tri-State on a per channel basis for the ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT XRT83SL28 IGURE THE DMO5 109 TNEG4/CODE4 110 TPOS4/TDATA4 111 TCLK4 112 TNEG5/CODE5 113 TPOS5/TDATA5 114 TCLK5 115 RLOS5 116 RNEG5/LCV5 117 RPOS5/RDATA5 118 RCLK5 119 RLOS4 ...
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REV. 1.0.0 GENERAL DESCRIPTION................................................................................................. 1 APPLICATIONS........................................................................................................................................... IGURE OST ODE LOCK IAGRAM OF THE IGURE ARDWARE ODE LOCK ..................................................................................................................................................... 3 FEATURES PRODUCT ORDERING INFORMATION.................................................................................................. ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. IGURE IMPLIFIED LOCK IAGRAM OF 3.1.2 REMOTE LOOPBACK ................................................................................................................................................ IGURE IMPLIFIED LOCK IAGRAM OF 3.1.3 DIGITAL ...
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REV. 1.0.0 PIN DESCRIPTIONS HOST MODE INTERFACE SERIAL MICROPROCESSOR INTERFACE AME IN YPE SCLK 90 I SDI 92 I SDO 91 O Reset 28 I INT 100 O HW/Host 81 I 8-CHANNEL E1 ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT RECEIVER SECTION AME IN YPE RLOS7 61 O RLOS6 65 RLOS5 116 RLOS4 120 RLOS3 48 RLOS2 44 RLOS1 137 RLOS0 133 RCLK7 58 O RCLK6 62 RCLK5 119 RCLK4 ...
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REV. 1.0.0 RECEIVER SECTION AME IN YPE RTIP7 75 I RTIP6 87 RTIP5 94 RTIP4 106 RTIP3 34 RTIP2 22 RTIP1 15 RTIP0 3 RRING7 76 I RRING6 86 RRING5 95 RRING4 105 RRING3 33 RRING2 ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT TRANSMITTER SECTION AME IN YPE TPOS7 70 I TPOS6 67 TPOS5 114 TPOS4 111 TPOS3 39 TPOS2 42 TPOS1 139 TPOS0 142 TNEG7 71 I TNEG6 68 TNEG5 113 TNEG4 ...
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REV. 1.0.0 POWER AND GROUND (HOST AND HARDWARE MODES AME IN YPE TVDD7 79 PWR TVDD6 83 TVDD5 98 TVDD4 102 TVDD3 30 TVDD2 26 TVDD1 11 TVDD0 7 RVDD2 127 PWR RVDD1 54 DVDD2 129 ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT HARDWARE MODE INTERFACE AME IN YPE SR/ TERSEL1 125 I TERSEL0 124 TCLKinv 107 I RCLKinv 74 I LBM1 56 I LBM0 57 JASEL1 20 I JASEL0 21 ...
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REV. 1.0 AME IN YPE FIFOS 19 I HW/Host 81 I Reset 28 I CHLB3 89 I CHLB2 90 CHLB1 91 CHLB0 92 RLOS7 61 O RLOS6 65 RLOS5 116 RLOS4 120 RLOS3 48 RLOS2 44 ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT AME IN YPE RNEG/LCV7 60 O RNEG/LCV6 64 RNEG/LCV5 117 RNEG/LCV4 121 RNEG/LCV3 49 RNEG/LCV2 45 RNEG/LCV1 136 RNEG/LCV0 132 RTIP7 75 I RTIP6 87 RTIP5 94 RTIP4 106 RTIP3 ...
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REV. 1.0 AME IN YPE TPOS7 70 I TPOS6 67 TPOS5 114 TPOS4 111 TPOS3 39 TPOS2 42 TPOS1 139 TPOS0 142 TNEG7/CODE7 71 I TNEG6/CODE6 68 TNEG5/CODE5 113 TNEG4/CODE4 110 TNEG3/CODE3 38 TNEG2/CODE2 41 TNEG1/CODE1 ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 1.0 RECEIVE PATH LINE INTERFACE The receive path of the XRT83SL28 LIU consists of 8 independent E1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A ...
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REV. 1.0.0 1.2 Peak Detector/Data Slicer In the receive path, the line signal is coupled into the RTIP and RRing pins via a 1:1 transformer and are converted into digital pulses by an adaptive data slicer. Clock and data ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT ABLE P ARAMETER RCLK Rise Time (10% to 90%) with 25pF Loading RCLK Fall Time (90% to 10%) with 25pF Loading N : VDD=3.3V ±5%, T =25°C, Unless Otherwise Specified ...
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REV. 1.0.0 1.5.1 RLOS (Receiver Loss of Signal) The XRT83SL28 supports both G.775 or ETSI-300-233 RLOS detection scheme. In G.775 mode, RLOS is declared when the received signal is less than 320mV for 32 consecutive pulse periods (typical). The ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 1.7 HDB3 Decoder In single rail mode, RPOS is the output of decoded AMI or HDB3 signals and RNEG is the LCV output. HDB3 data is defined as any block of 4 successive ...
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REV. 1.0 IGURE UAL AIL ODE ITH A RCLK RPOS 0 RNEG 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT F R "0011" P IXED EPEATING ATTERN XRT83SL28 0 1 ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.0 TRANSMIT PATH LINE INTERFACE The transmit path of the XRT83SL28 LIU consists of 8 independent E1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A ...
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REV. 1.0 ABLE P ARAMETER TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time (10% to 90%) TCLK Fall Time (90 VDD=3.3V ±5%, T =25°C, Unless Otherwise ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 2.4 TAOS (Transmit All Ones) The XRT83SL28 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. If TAOS is enabled, the Transmitter outputs will ...
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REV. 1.0.0 2.8 Line Termination (TTIP/TRING) The output stage of the transmit path generates standard bipolar signals to the line for both E1 (75 Ohm) coaxial cable and E1 (120 Ohm) twisted pair. The XRT83L28 has built-in output impedance ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.0 E1 APPLICATIONS This applications section describes common E1 system considerations along with references to application notes available for reference where applicable. 3.1 Loopback Diagnostics The XRT83SL28 supports several loopback modes for diagnostic ...
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REV. 1.0.0 3.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The receive input data at RTIP/RRING is ignored while valid transmit output data continues ...
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... System designers can achieve this by implementing common redundancy schemes with the XRT83SL28 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. RLOS and DMO If an RLOS or DMO condition occurs, the XRT83SL28 reports the alarm to the individual status registers on a per channel basis ...
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REV. 1.0.0 3.2.3 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the backup card will not ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.2.5 Transmit Interface with N+1 Redundancy For N+1 redundancy, the transmitters on all cards can be programmed for internal impedance. transmitters on the backup card do not have to be tri-stated. To swap ...
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REV. 1.0.0 3.2.6 Receive Interface with N+1 Redundancy For N+1 redundancy, the receivers on all cards can be programmed for internal impedance. The receivers on the backup card do not have to be tri-stated. To swap the primary card, ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 3.3 Power Failure Protection For 1:1 or 1+1 line card redundancy in E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in ...
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REV. 1.0.0 4.0 SERIAL MICROPROCESSOR INTERFACE BLOCK The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the LIU. Optional pins such as SDO, INT, and RESET allow the ability to read back ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT 4.2 16-Bit Serial Data Input Description The serial data input is sampled on the rising edge of SCLK. In read-back mode, the serial data output is updated on the falling edge of SCLK. ...
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REV. 1.0.0 T ABLE R ADDR YPE Global Control Register for All 8 Channels (0x00h) 0 0x00 R/W GIE SR/DR Revision ID (See Bit Description) 1 0x01 RO 2 0x02 RO Device ID (See Bit Description) ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T ABLE R ADDR YPE Channel 6 Control Register (0x1Ch - 0x1Fh) 28 0x1C R/W Reserved RLAM6 29 0x1D R/W Reserved SRESET6 30 0x1E RUR Reserved Reserved 31 0X1F RO ...
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REV. 1.0 ABLE G LOBAL AME D7 GIE Global Interrupt Enable The global interrupt enable is used to enable/disable all interrupt activity for all 8 channels. This bit must be set "High" for ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT ABLE AME D7 Revision The revision "ID" of the XRT83SL28 LIU is used to enable software "ID" to identify which revision of silicon is currently being tested. ...
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REV. 1.0.0 T 10: M ABLE HANNEL ONTROL EGISTER AME D5 ARAOS_n Automatic Receive All Ones If ARAOS_n is selected, an all ones pattern will be sent to the RPOS/RNEG outputs if the ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T 11: M ABLE HANNEL ONTROL EGISTER AME D7 Reserved This Register Bit is Not Used D6 SRESET_n Software Reset By setting this bit to "1" for ...
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REV. 1.0.0 T 12: M ABLE HANNEL ONTROL EGISTER AME D5 AISI_n Alarm Indication Signal Interrupt Status "0" Change "1" = Change in Status Occured D4 DMOI_n Driver Monitor Output Interrupt ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT HANNEL ONTROL EGISTER AME D3 RLOSS_n Receiver Loss of Signal Alarm Status The receiver loss of signal detection is always active regardless if the interrupt generation is ...
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REV. 1.0.0 ELECTRICAL CHARACTERISTICS Storage Temperature Operating Temperature Supply Voltage Vin T 15 ABLE VDD=3.3V ±5 ARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage IOH=2.0mA Output Low Voltage IOL=2.0mA Input ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT T ABLE VDD=3.3V ±5 ARAMETER Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (short haul with cable loss) ...
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REV. 1.0 ABLE VDD=3.3V ±5 ARAMETER AMI Output Pulse Amplitude 75 Ω 120 Ω Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Output Return ...
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XRT83SL28 8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT ORDERING INFORMATION P N RODUCT UMBER XRT83SL28IV PACKAGE DIMENSIONS 109 144 A Seating Plane ACKAGE 144 LEAD TQFP 144 LEAD THIN QUAD FLAT PACK ( 1.4 mm ...
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... EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...