XRT83SL28ES Exar, XRT83SL28ES Datasheet - Page 20

• Manufacturer Part Number: XRT83SL28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
In single rail mode, RPOS is the output of decoded AMI or HDB3 signals and RNEG is the LCV output. HDB3
data is defined as any block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V
pulses are of opposite polarity to acheive zero DC offsey. If the HDB3 decoder is selected, the receive path
removes the V and B pulses so that the original data is output to RPOS.
The XRT83SL28 has the ability to send an All Ones signal to RPOS if ARAOS is enabled in the appropriate
channel register. If ARAOS is enabled and an RLOS condition occurs, the Receiver outputs will generate a
single rail All Ones pattern. When RLOS clears, the All Ones pattern ends and the Receive path returns to
normal operation. For TAOS in the transmit direction, see the Transmit Section of this datasheet. A simplified
block diagram of the ATAOS function is shown in Figure 9.
The digital output data can be programmed to either single rail or dual rail formats. Figure 10 is a timing
diagram of a repeating "0011" pattern in single-rail mode. Figure 11 is a timing diagram of the same fixed
pattern in dual rail mode.
F
F
1.7
1.8
1.9
IGURE
IGURE
9. S
10. S
HDB3 Decoder
ARAOS (Automatic Receive All Ones)
RPOS/RNEG/RCLK
RCLK
RPOS
IMPLIFIED
INGLE
R
AIL
B
LOCK
M
ODE
0
D
IAGRAM OF THE
W
ARAOS
RLOS
ITH A
RPOS
RNEG
F
TAOS
IXED
0
R
ARAOS F
EPEATING
18
Rx
UNCTION
"0011" P
1
ATTERN
1
0
xr
REV. 1.0.0