XRT83SL28ES Exar, XRT83SL28ES Datasheet - Page 13

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XRT83SL28ES

Manufacturer Part Number
XRT83SL28ES
Description
Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH
Manufacturer
Exar
Datasheet

Specifications of XRT83SL28ES

Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
xr
REV. 1.0.0
HW/Host
RLOS7
RLOS6
RLOS5
RLOS4
RLOS3
RLOS2
RLOS1
RLOS0
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
CHLB3
CHLB2
CHLB1
CHLB0
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
FIFOS
Reset
N
AME
116
120
137
133
119
123
134
130
118
122
135
131
P
19
81
28
89
90
91
92
61
65
48
44
58
62
51
47
59
63
50
46
IN
T
YPE
O
O
O
I
I
I
I
FIFO Bit Depth Select Input
This pin is used to select the depth of the FIFO. By default, the FIFO is set to
32-Bit. To select a 64-Bit FIFO depth, this pin must be pulled "High". To meet
TBR12/13 applications, the FIFO size must be set to 64-bit.
N
Same as Host Mode.
Same as Host Mode.
Channel Loop Back Select
CHLB[3:0] are used to select a particular channel or all eight channels simulta-
neously for Loop Back mode. See pins LBM[1:0] for selecting various types of
Loop Back diagnostics.
"0000" = Channel 0
"0001" = Channel 1
"0010" = Channel 2
"0011" = Channel 3
"0100" = Channel 4
"0101" = Channel 5
"0110" = Channel 6
"0111" = Channel 7
"1111" = All Eight Channels
N
Same as Host Mode.
Same as Host Mode.
Same as Host Mode.
OTE
OTE
: Internally pulled "Low" with a 50kΩ resistor.
: CHLB3 (Pin 89) is internally pulled "High" with a 50kΩ Resistor.
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
11
D
ESCRIPTION
XRT83SL28

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