XRT83SL28ES Exar, XRT83SL28ES Datasheet - Page 8

• Manufacturer Part Number: XRT83SL28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

RECEIVER SECTION
XRT83SL28
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
RNEG/LCV7
RNEG/LCV6
RNEG/LCV5
RNEG/LCV4
RNEG/LCV3
RNEG/LCV2
RNEG/LCV1
RNEG/LCV0
RPOS7
RPOS6
RPOS5
RPOS4
RPOS3
RPOS2
RPOS1
RPOS0
RLOS7
RLOS6
RLOS5
RLOS4
RLOS3
RLOS2
RLOS1
RLOS0
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
N
AME
120
137
133
123
134
130
122
135
131
121
136
132
116
119
118
117
P
61
65
48
44
58
62
51
47
59
63
50
46
60
64
49
45
IN
T
YPE
O
O
O
O
Receive Loss of Signal
When a receive loss of signal occurs, the RLOS pin will go "High" for a mini-
mum of one RCLK cycle. RLOS will remain "High" until the loss of signal con-
dition clears. See the Receive Loss of Signal section of this datasheet for
more details.
Receive Clock Output
RCLK is the recovered clock from the incoming data stream. If the incoming
signal is absent, RCLK maintains its timing by using an internal master clock
as its reference. RPOS/RNEG data can be updated on either edge of RCLK
selected by RCLKinv in the appropriate global register.
N
RPOS/RDATA Output
Receive digital output pin. In dual rail mode, this pin is the receive positive
data output. In single rail mode, this pin is the receive non-return to zero (NRZ)
data output.
RNEG/LCV Output
In dual rail mode, this pin is the receive negative data output. In single rail
mode, this pin is a Line Code Violation indicator. If a line code violation or a bi-
polar violation occur, the LCV pin will pull "High" for a minimum of one RCLK
cycle. LCV will remain "High" until there are no more violations.
OTE
: RCLKinv is a global setting that applies to all 8 channels.
6
D
ESCRIPTION
xr
REV. 1.0.0