XRT83SL28ES Exar, XRT83SL28ES Datasheet - Page 37

• Manufacturer Part Number: XRT83SL28ES
• Description: Peripheral Drivers & Components - PCIs 8 CH E1 LIU SH
• Manufacturer: Exar

Specifications of XRT83SL28ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

xr
REV. 1.0.0
B
D7
D6
D5
D4
D3
D2
D1
D0
IT
RCLKinv
TCLKinv
JASEL1
JASEL0
SR/DR
FIFOS
CODE
N
GIE
AME
T
Global Interrupt Enable
The global interrupt enable is used to enable/disable all interrupt
activity for all 8 channels. This bit must be set "High" for the inter-
rupt pin to operate.
"0" = Disable all interrupt generation
"1" = Enable interrupt generation to the individual channel registers
Single Rail / Dual Rail Select
This bit is used to configure the receive outputs and transmit inputs
to single rail or dual rail data formats.
"0" = Dual Rail
"1" = Single Rail
Encoding / Decoding Select (Single Rail Mode Only)
This bit is used to select between AMI or HDB3.
"0" = HDB3
"1" = AMI
Receiver Clock Data
"0" = RPOS/RNEG data is updated on the rising edge of RCLK
"1" = RPOS/RNEG data is updated on the falling edge of RCLK
Transmitter Clock Data
"0" = TPOS/TNEG data is sampled on the falling edge of TCLK
"1" = TPOS/TNEG data is sampled on the rising edge of TCLK
FIFO Depth Select
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (Within the Jitter Attenuator Block). The delay of the
FIFO is typically equal to ½ the FIFO depth.
"0" = 32-bit FIFO
"1" = 64-bit FIFO
Jitter Attenuator Select
These bits are used to configure the Jitter Attenuator into the
Receive or Transmit path.
"00" = Disabled
"01" = Transmit Path
"10" = Receive Path
"11" = Disabled
ABLE
G
LOBAL
7: M
ICROPROCESSOR
C
ONTROL
R
EGISTER FOR
F
UNCTION
8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
R
35
EGISTER
A
LL
0
8 C
X
00
HANNELS
H
B
IT
D
(0
ESCRIPTION
X
00
H
)
Register
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XRT83SL28
(HW reset)
Default
Value
0
0
0
0
0
0
0
0