PCA9629PW,118 NXP Semiconductors, PCA9629PW,118 Datasheet
PCA9629PW,118
Specifications of PCA9629PW,118
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PCA9629PW,118 Summary of contents
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PCA9629 Fm+ I Rev. 1 — 29 February 2012 1. General description The PCA9629 and control required to drive a four phase stepper motor. PCA9629 is intended to be used with external high current drivers to drive ...
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... NXP Semiconductors Four general purpose I/Os: Configured to sense logic level outputs from optical interrupter photo transistor circuit Configured as outputs to drive (source/sink) LEDs or other loads Programmable interrupt Mask Control for input pins 4 5.5 V operation 1 MHz Fast-mode Plus (Fm SDA output for driving high capacitive buses ...
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... NXP Semiconductors 5. Block diagram PCA9629 SCL INPUT FILTER SDA POWER- RESET 200 kΩ RESET V SS MOTOR CONTROLLER STEPS, ROTATIONS AND PULSE WIDTH COUNTERS Remark: All I/Os are set to inputs at power-up and reset. Fig 1. PCA9629 block diagram PCA9629 Product data sheet AD0 AD1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. Symbol AD0 AD1 RESET V SS OUT3 OUT2 OUT1 OUT0 INT SCL SDA V DD PCA9629 Product data sheet AD0 AD1 6 RESET Pin configuration for TSSOP16 ...
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... NXP Semiconductors 7. Functional description Refer to 7.1 Device address Following a START condition, the bus master must send the target slave address followed by a read or write operation. The slave address of the PCA9629 is shown in Slave address pins AD1 and AD0 choose one of 16 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and AD0 ...
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... NXP Semiconductors 7.2 Command register Following the successful acknowledgement of the slave address and a write bit, the bus master sends a byte to the PCA9629. This byte is stored in the Command register. Fig 4. At power-up, the Command register defaults to 80h, with the AI bit set to ‘1’ and the lowest seven bits set to ‘ ...
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... NXP Semiconductors Table 5. Register summary …continued Register Name number 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h ...
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... NXP Semiconductors 7.3.1 MODE — Mode register Table 6. Legend: * default value. Address 00h 7.3.1.1 Disable interrupt output pin (bit 5) This feature is useful when the host/micro/master does not want the INT pin to toggle when interrupts occur. Within PCA9629, when interrupts are enabled and interrupt event occurs, the actions related to the interrupt event are still carried out ...
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... NXP Semiconductors 7.3.2 SUBADR1 to SUBADR3 — I Table 7. Legend: * default value. Address 01h 02h 03h Subaddresses are programmable through the I E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding bits [3:1] in MODE register is equal to 0). Once subaddresses have been programmed to their right values, bits [3:1] (MODE register) must be set to logic 1 in order to have the device acknowledging these addresses ...
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... NXP Semiconductors 7.3.4 Watchdog timer The purpose of the watchdog timer is to recover the PCA9629 if the system it is used in enters an erroneous state. When the timer times out, the watchdog generates an interrupt to the host controller and, if programmed for reset, resets PCA9629 if the user program fails to ‘ ...
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... NXP Semiconductors 7.3.4.2 WDCNTL — WatchDog Control register Table 10. Legend: * default value. Address 06h [1] Use bit 4 to clear this bit. [2] Reading WDCNTL register clears this bit. This register controls the operation of the watchdog timer. Watchdog timer can be enabled by setting the WDEN bit of this register. WDEN is a set-only bit. Once set (enabled), this bit cannot be cleared by software ...
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... NXP Semiconductors 7.3.5 GPIOs and interrupts 7.3.5.1 IP — Input Port register This register is read-only. They reflect the incoming logic levels of the port pins P0 to P3, regardless of whether the pin is defined as an input or an output by the I/O configuration register. Writes to this register have no effect. Table 11. ...
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... NXP Semiconductors 7.3.5.4 IOC — I/O Configuration register The lower four bits of this register configures the direction of the I/O pins bit in [3:0] is set (written with logic 1), the corresponding port pin is enabled as an input with high-impedance output driver. If the bit is cleared (written with logic 0), the corresponding port pin is enabled as an output. At reset, the device’ ...
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... NXP Semiconductors 7.3.5.6 CLRINT — Clear Interrupts register Interrupt flags can be cleared by bits [3:0] when set to logic 1. Table 16. Legend: * default value. Address 0Ch 7.3.5.7 INTMODE — Interrupt Mode register When interrupt(s) are enabled, bits [3:0] determine whether rising edge or falling edge of signal causes the interrupt to be generated. Interrupts are latched and flag(s) are set in the corresponding bits of INTSTAT register ...
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... NXP Semiconductors IOC[0] MSK[0] RISING EDGE DETECTOR P0 FALLING EDGE DETECTOR IOC[3] MSK[3] RISING EDGE DETECTOR P3 FALLING EDGE DETECTOR Fig 6. PCA9629 interrupt logic 7.3.6 Interrupt based motor control Interrupt mechanisms from GPIOs 0 and 1 (INTP0 and INTP1) can be used to control the motor operation. Interrupts from GPIOs 2 and 3 are not used for motor control. They behave as normal GPIO interrupts ...
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... NXP Semiconductors 7.3.6.1 INT_ACT_SETUP — Interrupt Action Setup control register Table 18. Legend: * default value. Address 0Eh If the interrupt based control is disabled, then values programmed in the following three registers (INT_MTR_SETUP, INT_ES_SETUP and INT_AUTO_CLR) have no effect on the motor operation. Bit 4 of this register determines whether the values programmed in EXTRASTEPS0 and ...
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... NXP Semiconductors 7.3.6.3 INT_ES_SETUP — Interrupt Extra Steps Setup control register Table 20. Legend: * default value. Address 10h This register can be used to enable / disable the extra steps feature for each interrupt. Extra steps feature is used to make the motor rotate a specified amount of steps/rotations from the point of an interrupt occurrence. ...
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... NXP Semiconductors Example: This example assumes that two position sensors are located spaced apart and a drive mechanism is needed to move an object back and forth between these two sensors. movement of the object toward one of the sensors. Logic level output of one sensor is connected to input pin P0 and the other to P1. P0 and P1 are configured as inputs. ...
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... NXP Semiconductors 7.3.7 SETMODE — output state on STOP control register This register determines the condition of motor output pins when STOPPED, one of logic 0 or Hold (last state). Table 22. Legend: * default value. Address 12h 7.3.8 PHCNTL — Phase Control register This register is used to configure the phase of the output waveforms at the output ports OUT0 to OUT3 to drive the motor coils (with external high current drivers) ...
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... NXP Semiconductors 7.3.10 CWPWL, CWPWH — Clockwise step pulse width register This register determines the step pulse width used for the phase sequence output waveforms during ClockWise (CW) rotation. Table 25. Legend: * default value. Address 16h 17h This register sets the pulse width value between 3 s and 3145 ms (5 %). ...
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... NXP Semiconductors 7.3.11 CCWPWL, CCWPWH — Counter-clockwise step pulse width register This register determines the step pulse width used for the phase sequence output waveforms during Counter-ClockWise (CCW) rotation. Table 27. Legend: * default value. Address 18h 19h The 16-bit value sets the pulse width between 3 s and 3145 ms (5 %). ...
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... NXP Semiconductors 7.3.12 CWSCOUNTL, CWSCOUNTH — Number of clockwise steps register This register determines the number of steps the motor should turn in clockwise direction. Table 29. Legend: * default value. Address 1Ah 1Bh 7.3.13 CCWSCOUNTL, CCWSCOUNTH — Number of counter-clockwise steps register This register determines the number of steps the motor should turn in counter-clockwise direction ...
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... NXP Semiconductors 7.3.16 EXTRASTEPS0, EXTRASTEPS1 — Extra steps count for INTP0, INTP1 control register Table 33. Legend: * default value. Address 22h 23h This register has no effect if the interrupt based motor control is disabled or if the EXTRASTEPS feature for that interrupt is disabled. When EXTRASTEPS feature is selected using INT_ES_SETUP register bits [1:0], the 8-bit value in this register is used to determine the number of steps or rotations to be overdriven ...
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... NXP Semiconductors Table 35. Register value [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110, 1111 RMPCNTL[5:4] enables/disables the speed ramp-up during starting of the motor and speed ramp-down during stopping of the motor. The RMPCNTL[3:0] defines the acceleration/decelerating rate of the ramp control. If the value is small, the PWM width decrement (accelerating)/increment (decelerating) is slower ...
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MCNTL[ ramp-up operation 98.304 97.536 OUT0 ms ms 98.112 OUT1 ms 97.92 OUT2 ms 97.728 OUT3 ms Example shown is one-phase drive ...
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... NXP Semiconductors During ramp-up and ramp-down phase of operation, the interrupt based controls do not affect the motor run. An interrupt can happen during ramp-up or ramp-down and it gets registered in the chip. Once the ramp-up operation is finished, then the interrupt is acted upon. A stop request from the microcontroller (writing MCNTL[7] to ‘0’) is the only event that affects the motor operation during ramp-up and ramp-down ...
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... NXP Semiconductors 7.3.19 MCNTL — Motor control register This register acts like the master control panel for driving the motor. It determines the type of motor operation and controls the starting/stopping of the motor. The registers from address 0Eh (INT_ACT_SETUP) to 25h (LOOPDLY) are referred to as the motor parameter registers ...
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... NXP Semiconductors 7.3.19.2 MCNTL[5]: hard stop The ‘hard stop’ feature is only applicable for stop requests issued by the micro. It does not affect the interrupt based stop mechanism. This feature is used to stop the motor immediately when the micro issues a stop request. Hard stop feature has a higher priority over ramp down ...
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... NXP Semiconductors 7.4 Motor coil excitation Initially, after a power-up of the device, when the motor is started for the first time, the first coil that is energized is OUT0 (if the motor is turning in the clockwise direction), or OUT3 (if the motor is turning in the counter clockwise direction). This very first step (after a power-up) is not counted towards the number steps the motor is required to move (it is the reference step) ...
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... NXP Semiconductors 7.7 Software reset The Software Reset Call allows all the devices in the I state value through a specific formatted I implies that the I The maximum wait time after software reset (typical). The SWRST Call function is defined as the following START command is sent by the I 2 ...
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... NXP Semiconductors 7.9 Phase sequence generator The PCA9629 phase sequence generator uses the on-chip oscillator and control logic to generate logic waveforms needed to support the following three types of stepper motor drive formats: • One-phase drive, also called ‘wave drive’ • Two-phase drive • ...
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... NXP Semiconductors 7.9.2 Two-phase drive In two-phase drive method, two windings are energized at any given time. In case of two-phase drive, the torque output of the unipolar wound motor is lower than the bipolar motor (for motors with the same winding parameters) since the unipolar motor uses only the available winding, while the bipolar motor uses the entire winding ...
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... NXP Semiconductors Fig 13. Half-step drive sequence waveforms Table 40. Winding Winding D Winding C Winding B Winding A PCA9629 Product data sheet step pulses output D D output C C output B B output A A rotor position Four step stepper motor run with half-step waveforms increases the number of steps to eight. ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 16. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 10. Application design-in information 3.3 V 1.6 kΩ 1.6 kΩ 1.1 kΩ MASTER CONTROLLER INT RST Device address configured as 0100 0000b for this example. Fig 18. Typical application 10.1 Stepper motor coil driver considerations When choosing a motor and coil driver circuit for an application necessary to choose the coil driver such that the minimum expected drive strength of the coil driver over the anticipated operating conditions exceeds the minimum coil current in the application ...
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... NXP Semiconductors 10.2 Considerations when using GPIO pins inputs For proper operation of GPIO pins as inputs, the signals at the inputs must be free from any glitches or noise. The signals must be logic level inputs. For example, outputs from sensors must provide logic level signals at the input pins of PCA9629 ...
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... NXP Semiconductors • Before the specified number of rotations is completed in the CCW direction, if interrupt P1 happens, then it again reverses its rotation right away and start rotating in the CW direction for the specified number of rotations. • other interrupt happens, the motor finishes executing the specified number of rotations in the CW direction and then starts to ramp down ...
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... NXP Semiconductors Table 42. Static characteristics Symbol Parameter OUT0 to OUT3 outputs I LOW-level output current OL I total LOW-level output current OL(tot) V HIGH-level output voltage I/Os I LOW-level output current OL I total LOW-level output current OL(tot) V HIGH-level output voltage ...
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... NXP Semiconductors 13. Dynamic characteristics Table 43. Dynamic characteristics Oscillator frequency = 1 MHz Symbol Parameter f SCL clock frequency SCL t bus free time between a BUF STOP and START condition t hold time (repeated) START HD;STA condition t set-up time for a repeated SU ...
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... NXP Semiconductors The internal glitch filter rejects any LOW pulse less than 1 s. The system level reset pulse should be > 4 s for the chip to guarantee [9] reset condition. SDA t BUF t LOW SCL t HD;STA P S Fig 21. Definition of timing SCL SDA RESET rec(rst Fig 22 ...
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... NXP Semiconductors 14. Test information Fig 24. Test circuitry for switching times for GPIO pins Fig 25. Test circuitry for switching times for SDA and SCL PCA9629 Product data sheet V I PULSE GENERATOR R = load resistance load capacitance includes jig and probe capacitance. ...
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... NXP Semiconductors 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 46. Acronym AI CCW CDM CMOS CPU CW DMOS DUT ESD FET Fm+ GPIO HBM HVAC I/O 2 C-bus I IC ...
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... NXP Semiconductors Table 46. Acronym NMOS MSB PCB pps PWM POR 19. Revision history Table 47. Revision history Document ID Release date PCA9629 v.1 20120229 PCA9629 Product data sheet Abbreviations …continued Description Negative-channel Metal-Oxide Semiconductor Most Significant Bit Printed-Circuit Board pulses per second Pulse Width Modulator ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... For sales office addresses, please send an email to: PCA9629 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Command register . . . . . . . . . . . . . . . . . . . . . . 6 7.3 Register definitions . . . . . . . . . . . . . . . . . . . . . . 6 7.3.1 MODE — Mode register . . . . . . . . . . . . . . . . . . 8 7.3.1.1 Disable interrupt output pin (bit ...
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... NXP Semiconductors 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 43 16 Handling information Soldering of SMD packages . . . . . . . . . . . . . . 44 17.1 Introduction to soldering . . . . . . . . . . . . . . . . . 44 17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 44 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 44 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 45 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 46 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 47 20 Legal information 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 48 20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 20.4 Trademarks Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2 Fm+ I ...