PCA9629PW,118 NXP Semiconductors, PCA9629PW,118 Datasheet - Page 40

• Manufacturer Part Number: PCA9629PW,118
• Description: Motor / Motion / Ignition Controllers & Drivers I2C-bus Stepper motor controller
• Manufacturer: NXP Semiconductors
• Type: Stepper Motor Controllerr

Specifications of PCA9629PW,118

• Rohs: yes
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6 mA
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16
• Factory Pack Quantity: 2500

NXP Semiconductors
13. Dynamic characteristics
Table 43.
V
[1]
[4]
[6]
[7]
[8]
PCA9629
Product data sheet
Oscillator frequency = 1 MHz
[2]
[3]
[5]
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RESET
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
d(o)
w(rst)
rec(rst)
DD
= 4.5 V to 5.5 V; V
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
t
t
In order to bridge the undefined region of the SCL falling edge, a master device must internally provide a hold time of at least 300 ns for
the SDA signal (refer to the V
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
The time delay from one of the P[1:0] inputs edge changes to the motor control outputs OUT[3:0] change. Typical value = 6.5 s.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
Parameter
SCL clock frequency
bus free time between a
STOP and START condition
hold time (repeated) START
condition
set-up time for a repeated
START condition
set-up time for STOP
condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL
signals
rise time of both SDA and
SCL signals
pulse width of spikes that
must be suppressed by the
input filter
output delay time
reset pulse width
reset recovery time
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
Dynamic characteristics
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
SS
= 0 V; T

IL
5 % at 25
of the SCL signal).
amb
f
.
=

40

All information provided in this document is subject to legal disclaimers.
C (see
interrupt based
Conditions
motor control
latency

C to +85
Rev. 1 — 29 February 2012
Figure

C; unless otherwise specified.
23).
[4][5]
[1]
[2]
[3]
[7]
[8]
[9]
Standard-mode
Min
250
4.7
4.0
4.7
4.0
4.7
4.0
0.3
0.3
5.7
0
0
1
-
-
-
-
I
2
C-bus
1000
Max
3.45
3.45
100
300
7.4
50
4
1
-
-
-
-
-
-
-
-
Fm+ I
0.1C
0.1C
Fast-mode
20 +
20 +
Min
100
1.3
0.6
0.6
0.6
0.1
0.1
1.3
0.6
5.7
2
I
0
0
1
-
-
C-bus stepper motor controller
2
f
C-bus
) for the SDA output stage is specified at
b
b
[6]
[6]
Max
400
300
300
0.9
0.9
7.4
50
4
1
-
-
-
-
-
-
-
-
Fast-mode Plus
0.26
0.26
0.26
0.05
0.05
0.26
Min
0.5
0.5
5.7
50
PCA9629
0
0
1
-
-
-
-
© NXP B.V. 2012. All rights reserved.
I
2
C-bus
1000
Max
0.45
0.45
120
120
7.4
50
4
1
-
-
-
-
-
-
-
-
40 of 51
Unit
kHz
s
s
s
s
ns
s
s
ns
s
s
ns
ns
ns
s
s
ms