PCA9629PW,118 NXP Semiconductors, PCA9629PW,118 Datasheet - Page 6

• Manufacturer Part Number: PCA9629PW,118
• Description: Motor / Motion / Ignition Controllers & Drivers I2C-bus Stepper motor controller
• Manufacturer: NXP Semiconductors
• Type: Stepper Motor Controllerr

Specifications of PCA9629PW,118

• Rohs: yes
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6 mA
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16
• Factory Pack Quantity: 2500

NXP Semiconductors
Table 5.
PCA9629
Product data sheet
Register
number
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Register summary
D5 D4 D3 D2 D1 D0 Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7.2 Command register
7.3 Register definitions
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Following the successful acknowledgement of the slave address and a write bit, the bus
master sends a byte to the PCA9629. This byte is stored in the Command register.
At power-up, the Command register defaults to 80h, with the AI bit set to ‘1’ and the lowest
seven bits set to ‘0’. The lowest six bits are used as a pointer to determine which register
will be accessed. Only a command register code with the six least significant bits equal to
the 39 allowable values as defined in
Reserved or undefined command codes are not acknowledged.
The most significant bit of the Command register is for Auto-Increment. If the
Auto-Increment flag is set, the six low-order bits of the Control register are automatically
incremented after a read or write. This allows the user to program the registers
sequentially. The contents of these bits will roll over to ‘00 0000’ after the last register
(address = 26h) is accessed. Only the six least significant bits are affected by the AI flag.
Unused bits must be programmed with zeroes.
Fig 4.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Command register
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
All information provided in this document is subject to legal disclaimers.
MODE
SUBADR1
SUBADR2
SUBADR3
ALLCALLADR
WDTOI
WDCNTL
IP
INTSTAT
OP
IOC
MSK
CLRINT
INTMODE
INT_ACT_SETUP
INT_MTR_SETUP
Rev. 1 — 29 February 2012
AI
1
Auto-Increment
0
-
D5
0
D4
0
Type
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read only
read only
read/write
read/write
read/write
write only
read/write
read/write
read/write
register number
Table 5 “Register summary”
D3
0
D2
0
D1
0
Function
Mode register
I
I
I
All Call I
Watchdog time-out interval register
Watchdog control register
Input Port register
Interrupt status register
Output Port register
I/O Configuration register
Mask interrupt register
Clear interrupts
Interrupt mode register
Interrupt action setup control register
Interrupt motor setup control register
Fm+ I
2
2
2
D0
C-bus subaddress 1
C-bus subaddress 2
C-bus subaddress 3
0
default at power-up
or after RESET
2
C-bus stepper motor controller
2
C-bus address
002aad906
are acknowledged.
PCA9629
© NXP B.V. 2012. All rights reserved.
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