PCA9629PW,118 NXP Semiconductors, PCA9629PW,118 Datasheet - Page 12

• Manufacturer Part Number: PCA9629PW,118
• Description: Motor / Motion / Ignition Controllers & Drivers I2C-bus Stepper motor controller
• Manufacturer: NXP Semiconductors
• Type: Stepper Motor Controllerr

Specifications of PCA9629PW,118

• Rohs: yes
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6 mA
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16
• Factory Pack Quantity: 2500

NXP Semiconductors
PCA9629
Product data sheet
7.3.5.1 IP — Input Port register
7.3.5.2 INTSTAT — Interrupt Status register
7.3.5.3 OP — Output Port register
7.3.5 GPIOs and interrupts
This register is read-only. They reflect the incoming logic levels of the port pins P0 to P3,
regardless of whether the pin is defined as an input or an output by the I/O configuration
register. Writes to this register have no effect.
Table 11.
Legend: * default value ‘X’ is determined by the externally applied logic level.
This register reflects the status of an interrupt. INTSTAT is a read-only register.
INTP0 to INTP3 interrupt caused by input port pins P0 to P3, respectively.
Table 12.
Legend: * default value.
Upon power-up or activation of hardware reset by RESET pin, INTSTAT register bits [3:0]
are cleared (= 0), thus clearing the interrupt flags. Change in logic level at GPIO pins
P0 to P3 configured as inputs will cause generation of interrupt when not masked using
MSK register. The corresponding flag bit in this register is set and latched until cleared.
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by IOC register. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the
output selection, not the actual pin value. Only the lower four bits are used and P0 to P3
are affected by this register.
Table 13.
Legend: * default value.
Address
07h
Address
08h
Address
09h
IP - Input Port register (address 07h) bit description
INTSTAT - Interrupt status register (address 08h) bit description
OP - Output Port register (address 09h) bit description
Register
Register
INTSTAT
Register
IP
OP
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 February 2012
Bit
3:0
Bit
3:0
7:4
7:4
Bit
7:4
3:0
read only
read only
-
R/W
Access
Access
Access
-
read only
Value
0h*
Xh*
Value
0000*
0000*
Value
0*
1
0*
1
0*
1
0*
1
0*
Description
reserved
reflects incoming logic levels of I/O P0 to P3
Description
reserved
reflects outgoing logic levels of I/O P0 to P3
Fm+ I
Description
reserved
INTP3 flag set
INTP3 flag clear
INTP2 flag set
INTP2 flag clear
INTP1 flag set
INTP1 flag clear
INTP0 flag set
INTP0 flag clear
2
C-bus stepper motor controller
PCA9629
© NXP B.V. 2012. All rights reserved.
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