PCA9629PW,118 NXP Semiconductors, PCA9629PW,118 Datasheet - Page 30

• Manufacturer Part Number: PCA9629PW,118
• Description: Motor / Motion / Ignition Controllers & Drivers I2C-bus Stepper motor controller
• Manufacturer: NXP Semiconductors
• Type: Stepper Motor Controllerr

Specifications of PCA9629PW,118

• Rohs: yes
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 6 mA
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16
• Factory Pack Quantity: 2500

NXP Semiconductors
PCA9629
Product data sheet
7.7 Software reset
7.8 Interrupt output
The Software Reset Call allows all the devices in the I
state value through a specific formatted I
implies that the I
The maximum wait time after software reset is 1 ms (typical).
The SWRST Call function is defined as the following:
The open-drain active LOW interrupt is activated by the following two mechanisms:
The interrupt INT pin output can be enabled or disabled using MODE register bit [5]
(0 = enable; 1 = disable). The interrupt flag bit is set in the INTSTAT register when one of
the interrupts is generated from P0 to P3.
Remark: If the state of the pin does not match the contents of the Input port register,
changing an I/O from an output to an input may cause a false interrupt to occur.
1. A START command is sent by the I
2. The reserved General Call I
3. The PCA9629 device(s) acknowledge(s) after seeing the General Call address
4. Once the General Call address has been sent and acknowledged, the master sends
5. Once the right byte has been sent and correctly acknowledged, the master sends a
•
•
(write) is sent by the I
‘0000 0000’ (00h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to
the I
one byte. The value of the byte must be equal to 06h. The PCA9629 acknowledges
this value only. If the byte is not equal to 06h, the PCA9629 does not acknowledge it.
If more than one byte of data is sent, the PCA9629 does not acknowledge anymore.
STOP command to end the software reset sequence: the PCA9629 then resets to the
default value (power-up value) and is ready to be addressed again within the specified
bus free time. If the master sends a Repeated START instead, no reset is performed.
The I
time) as a ‘Software Reset Abort’. The PCA9629 does not initiate a software reset.
Watchdog timer: If the watchdog timer is enabled and the timer times out, then an
interrupt is generated and the watchdog interrupt flag bit [3] is set in the watchdog
control register (WDCNTL).
GPIOs: One or more of pins P0 to P3 can generate an interrupt if the following
conditions are met:
– The pin is configured as an input in the I/O configuration register (IOC).
– The interrupt from that pin is enabled in the mask interrupt register (MSK).
– The pin’s state change (rising edge or falling edge) is programmed to generate an
interrupt in the interrupt mode register (INTMODE).
2
2
C-bus master.
C-bus master must interpret a non-acknowledge from the PCA9629 (at any
All information provided in this document is subject to legal disclaimers.
2
C-bus is functional and that there is no device hanging the bus.
Rev. 1 — 29 February 2012
2
C-bus master.
2
C-bus address ‘0000 000’ with the R/W bit set to ‘0’
2
C-bus master.
2
C-bus command. To be performed correctly, it
Fm+ I
2
C-bus to be reset to the power-up
2
C-bus stepper motor controller
PCA9629
© NXP B.V. 2012. All rights reserved.
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