MCIMX255AJM4AR2 Freescale Semiconductor, MCIMX255AJM4AR2 Datasheet - Page 85

• Manufacturer Part Number: MCIMX255AJM4AR2
• Description: Processors - Application Specialized IMX25 1.2 AUTO
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX255AJM4AR2

• Core: ARM926EJ-S
• Processor Series: MCIMX25
• Maximum Clock Frequency: 400 MHz
• Instruction / Data Cache Memory: 16 KB
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.15 V to 1.52 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Interface Type: USB
• Memory Type: DDR2
• Minimum Operating Temperature: - 40 C

3.7.9
The FEC is designed to support both 10- and 100-Mbps Ethernet networks compliant with the IEEE 802.3
standard. An external transceiver interface and transceiver function are required to complete the interface
to the media. The FEC supports 10/100 Mbps MII (18 pins altogether), 10/100 Mbps RMII (ten pins,
including serial management interface) and the 10-Mbps-only 7-Wire interface (which uses seven of the
MII pins), for connection to an external Ethernet transceiver. All signals are compatible with transceivers
operating at a voltage of 3.3 V.
The following subsections describe the timing for MII and RMII modes.
3.7.9.1
The following subsections describe MII receive, transmit, asynchronous inputs, and serial management
signal timings.
3.7.9.1.4
The receiver functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
FEC_RX_CLK frequency.
Figure 55
the figure.
1
Freescale Semiconductor
M1
M2
M3
M4
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
ID
FEC_RXD[3:0] (inputs)
FEC_RX_CLK (input)
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
FEC_RX_CLK pulse width high
FEC_RX_CLK pulse width low
shows MII receive signal timings.
Fast Ethernet Controller (FEC) Timing
FEC MII Mode Timing
FEC_RX_DV
FEC_RX_ER
MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK)
i.MX25 Applications Processor for Automotive Products, Rev. 9
Figure 55. MII Receive Signal Timing Diagram
Characteristic
Table 62. MII Receive Signal Timing
M1
1
Table 62
M2
describes the timing parameters (M1–M4) shown in
M3
Min.
35%
35%
5
5
M4
Max.
65%
65%
—
—
FEC_RX_CLK period
FEC_RX_CLK period
Unit
ns
ns
85