MCIMX255AJM4AR2 Freescale Semiconductor, MCIMX255AJM4AR2 Datasheet - Page 92

• Manufacturer Part Number: MCIMX255AJM4AR2
• Description: Processors - Application Specialized IMX25 1.2 AUTO
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX255AJM4AR2

• Core: ARM926EJ-S
• Processor Series: MCIMX25
• Maximum Clock Frequency: 400 MHz
• Instruction / Data Cache Memory: 16 KB
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.15 V to 1.52 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Interface Type: USB
• Memory Type: DDR2
• Minimum Operating Temperature: - 40 C

1
2
3
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
4
1
2
92
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal.
max_rise_time(ID No IC9) + data_setup_time(ID No IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the I2CLK line is released.
C
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
b
IC10
IC11
IC12
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
= total capacitance of one bus line in pF.
ID
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
Table 70. I2C Module Timing Parameters: 1.8 V +/– 0.10 V
i.MX25 Applications Processor for Automotive Products, Rev. 9
Parameter
b
)
Min.
Standard Mode
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
-
-
-
1
Freescale Semiconductor
3.45
Max.
1000
300
400
-
-
-
-
-
-
-
-
2
Unit
pF
ns
ns
ns
s
s
s
s
s
s
s
s