AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 136

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

19. Two-Wire Serial Interface
136
AT89LP51RD2/ED2/ID2 Preliminary
The Two-Wire Interface (TWI) is a bi-directional 2-wire serial communication standard. It is
designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised
of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs
connected to them. The only external hardware needed to implement the bus is a single pull-up
resistor for each of the TWI bus lines. All devices connected to the bus have individual
addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. The
serial data transfer is limited to 400Kbit/s in standard mode. Various communication configura-
tions can be designed using this bus.
of the devices connected to the bus can be master or slave.
The Two-Wire Interface on the AT89LP51RD2/ED2/ID2 provides the following features:
Note:
Figure 19-1. Two-Wire Bus Configuration
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tristate their outputs, allowing the pull-up resistors to pull the line
high. Note that all AT89LP devices connected to the TWI bus must be powered in order to allow
any bus operation. The number of devices that can be connected to the bus is only limited by the
bus capacitance limit of 400 pF and the 7-bit slave address space.
• Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Fully Programmable Slave Address with General Call Support
SDA
SCL
The TWI is available on both the AT89LP51RD2 and AT89LP51ED2 where as it was not available
on the AT89C51RD2 and AT89C51ED2. The TWI is not available in the PDIP package.
Device 1
Figure
19-1, both bus lines are connected to the positive supply voltage through
Device 2
Figure 19-1
Device 3
shows a typical 2-wire bus configuration. Any
........
Device n
V
CC
R1
3714A–MICRO–7/11
R2