AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 34

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

5.2
5.3
34
Compatibility Mode
Multiply–Accumulate Unit (MAC)
AT89LP51RD2/ED2/ID2 Preliminary
Compatibility (12-Clock) mode is enabled by default from the factory or by setting the Compati-
bility User Fuse. In Compatibility mode instruction bytes are fetched every three system clock
cycles and the CPU operates with 6-state machine cycles and a divide-by-2 system clock for 12
oscillator periods per machine cycle. Standard instructions execute in1, 2 or 4 machine cycles.
I n s t r u c t i o n t i m i n g i n t h i s m o d e i s c o m p a t i b l e w i t h s t a n d a r d 8 0 5 1 s s u c h a s t h e
AT89C51RD2/ED2/ID2. In Compatibility mode there is no difference in timing between
instructions executed from internal versus external program memory.
Compatibility mode can be used to preserve the execution profiles of legacy applications. For a
summary of differences between Fast and Compatibility modes see
Examples of Compatibility mode instructions are shown in
Figure 5-2.
The AT89LP51RD2/ED2/ID2 includes a multiply and accumulate (MAC) unit that can signifi-
cantly speed up many mathematical operations required for digital signal processing. The MAC
unit includes a 16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional
multiply-accumulate operations on signed 16-bit input values. The MAC unit also includes a 1-bit
arithmetic shifter that will left or right shift the contents of the 40-bit MAC accumulator register
(M).
(A) 1-byte, 1-cycle instruction, e.g., INC A A
(B) 2-byte, 1-cycle instruction, e.g., ADD A, #data
(B) 2-byte, 1-cycle instruction, e.g., ADD A, #data
(C) 1-byte, 2-cycle instruction, e.g., INC DPTR
(C) 1-byte, 2-cycle instruction, e.g., INC DPTR
(D) MOVX (1-byte, 2-cycle)
(D) MOVX (1-byte, 2-cycle)
CLK
CLK
ALE
ALE
Instruction Execution Sequences in Compatibility Mode
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
READ OPCODE
READ OPCODE
READ OPCODE
READ OPCODE
READ
READ
OPCODE
OPCODE
(MOVX)
(MOVX)
READ OPCODE
READ OPCODE
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
S3
S3
S3
S3
S3
S3
S3
S3
S3
S3
READ NEXT
READ NEXT
OPCODE (DISCARD)
OPCODE (DISCARD)
S4
S4
S4
S4
S4
S4
S4
S4
S4
S4
READ NEXT
READ NEXT
OPCODE
OPCODE
(DISCARD)
(DISCARD)
READ 2ND
READ 2ND
BYTE
BYTE
ACCESS EXTERNAL MEMOR
ACCESS EXTERNAL MEMORY
ADDR
ADDR
S5
S5
S5
S5
S5
S5
S5
S5
S5
S5
READ NEXT
READ NEXT
OPCODE (DISCARD)
OPCODE (DISCARD)
S6
S6
S6
S6
S6
S6
S6
S6
S6
S6
FETCH
FETCH
S1
S1
S1
S1
S1
S1
NO
NO
DA
DATA
READ NEXT OPCODE AGAIN
READ NEXT OPCODE AGAIN
READ NEXT OPCODE
READ NEXT OPCODE
S2
S2
S2
S2
S2
S2
Figure
NO
NO
ALE
ALE
S3
S3
S3
S3
S3
S3
5-2.
FETCH
FETCH
NO
NO
S4
S4
S4
S4
S4
S4
OPCODE AGAIN
OPCODE AGAIN
Table 2-3 on page
READ NEXT
READ NEXT
READ NEXT
READ NEXT
S5
S5
S5
S5
S5
S5
OPCODE
OPCODE
AGAIN
AGAIN
S6
S6
S6
S6
S6
S6
3714A–MICRO–7/11
S1
S1
12.