AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 40

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

5.4.2
5.4.2.1
5.4.2.2
40
AT89LP51RD2/ED2/ID2 Preliminary
Data Pointer Operating Modes
DPTR Redirect
Index Disable
The Dual Data Pointers on the AT89LP51RD2/ED2/ID2 include three additional operating
modes that affect data pointer based instructions. These modes are controlled by bits in DSPR.
Note that these bits in DSPR should be cleared to zero, disabling these modes, before any calls
are made to the Flash API.Care must also be taken when interrupt routines use data pointers to
ensure that correct operation is saved/restored correctly.
The Data Pointer Redirect to B bit, DPRB (DSPR.0), allows MOVX and MOVC instructions to
use the B register as the data source/destination when the instruction references DPTR1 as
shown in
multiple operands from different RAM locations.
Table 5-8.
The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the
MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as
MOVC A, @DPTR with no indexing as shown in
routines that must fetch multiple operands from program memory. DPRB can change the MOVC
destination register from ACC to B, but has no effect on the MOVC index register.
Table 5-9.
DPRB
MVCD
0
0
1
1
0
0
1
1
Table 5-8
DPRB
DPS
MOVX @DPTR Operating Modes
0
1
0
1
MOVC @DPTR Operating Modes
0
1
0
1
and
A, @A+DPTR0
A, @A+DPTR0
A, @DPTR0
A, @DPTR1
A, @DPTR0
B, @DPTR1
A, @DPTR0
A, @DPTR0
Table
MOVX
MOVX
MOVX
MOVX
MOVC
MOVC
MOVC
MOVC
DPTR
DPTR
MOVX A, @DPTR
5-9. DPRB can improve the efficiency of routines that must fetch
DPS = 0
Equivalent Operation for MOVC A, @A+DPTR
A, @A+DPTR1
B, @A+DPTR1
Equivalent Operation for MOVX
A, @DPTR0
A, @DPTR1
A, @DPTR0
B, @DPTR1
A, @DPTR1
B, @DPTR1
/DPTR
/DPTR
MOVX
MOVX
MOVX
MOVX
MOVC
MOVC
MOVC
MOVC
Table
5-9. MVCD can improve the efficiency of
A, @A+DPTR1
B, @A+DPTR1
@DPTR0, A
@DPTR1, A
@DPTR0, A
@DPTR1, B
A, @DPTR1
B, @DPTR1
MOVC
MOVC
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
DPTR
DPTR
MOVX @DPTR, A
DPS = 1
A, @A+DPTR0
A, @A+DPTR0
@DPTR1, A
@DPTR0, A
@DPTR1, B
@DPTR0, A
A, @DPTR0
A, @DPTR0
3714A–MICRO–7/11
/DPTR
MOVX
MOVX
MOVX
MOVX
/DPTR
MOVC
MOVC
MOVC
MOVC