AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 148

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

.
Table 19-6.
148
Status
Code
(SSCS)
0x08
10h
18h
20h
28h
AT89LP51RD2/ED2/ID2 Preliminary
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
A START condition has
been transmitted
A repeated START
condition has been
transmitted
SLA+W has been
transmitted; ACK has been
received
SLA+W has been
transmitted; NOT ACK has
been received
Data byte has been
transmitted; ACK has been
received
Status Codes for Master Transmitter Mode
A REPEATED START condition is generated by writing the following value to SSCON:
After a repeated START condition (status 10h) the Two-wire Serial Interface can access the
same slave again, or a new slave without transmitting a STOP condition. Repeated START
enables the master to switch between slaves, Master Transmitter mode and Master Receiver
mode without losing control of the bus.
SSCON
Value
SSCON
Value
To/from SSDAT
Load SLA+W
Load SLA+W
Load SLA+R
Load data byte
No action
No action
No action
Load data byte
No action
No action
No action
Load data byte
No action
No action
No action
bit rate
bit rate
CR2
CR2
Application Software Response
SSIE
SSIE
1
1
STA
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
STO
STA
STA
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
To SSCON
SI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
STO
STO
1
0
AA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SI
SI
0
0
Next Action Taken by TWI Hardware
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
Data byte will be transmitted and ACK or NOT
ACK will be received
Repeated START will be transmitted
STOP condition will be transmitted and STO
flag will be reset
STOP condition followed by a START condition
will be transmitted and STO flag will be reset
AA
AA
X
X
bit rate
bit rate
CR1
CR1
bit rate
bit rate
3714A–MICRO–7/11
CR0
CR0