AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet - Page 49

• Manufacturer Part Number: AT89LP51ED2-20MU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20MU

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: VQFN-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Processor Series: AT89x
• Program Memory Type: Flash
• Factory Pack Quantity: 360

6.8
Table 6-7.
Table 6-8.
3714A–MICRO–7/11
CKRL
TPS
Symbol
Symbol
3-0
CKRL = 97H
Not Bit Addressable
Bit
CLKREG = AEH
Not Bit Addressable
Bit
7-0
System Clock Prescaler
Function
Clock Reload. CKRL holds the reload value for the 8-bit system clock prescaler. When CKRL = FFH the prescaler is
disabled and no division is used. For all other values, the prescaler counts up to FFH and is reloaded with the value of
CKRL on the overflow to 00H. Each overflow of the prescaler will toggle the system clock. Changes to CKRL will take
affect on the next overflow.
Function
Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2, PCA and the Watchdog
Timer. The prescaler is implemented as a 4-bit binary down counter. When the counter reaches zero it is reloaded with
the value stored in the TPS bits to give a division ratio between 1 and 16. By default TPS is set to 5 for counting every six
cycles (AT89C51RD2/ED2/ID2 compatibility). The prescaler is always enabled in Compatibility mode. In Fast mode the
prescaler is off by default and can be individually enabled for the peripherals through the CKCON0 and CKCON1 SFRs.
CKRL
CLKREG
CKRL7
TPS3
7
7
– Clock Reload Register
– Clock Register
The AT89LP51RD2/ED2/ID2 includes an 8-bit prescaler that allows the system clock to be
divided down from the selected clock source by even numbers in the range 4–1020 in X1 mode
and 2–510 in X2 mode. The prescaler can reduce power consumption by decreasing the opera-
tional frequency during non-critical periods. The prescaler is implemented as an 8-bit counter
with reload. Upon overflow from FFH to 00H the counter is reloaded with the value of the CKRL
register. When CKRL = FFH the prescaler is disabled. The resulting system frequency is given
by the following equations where f
value of CKCON0.0:
The clock divider will prescale the clock for the CPU and all peripherals. The value of CKRL may
be changed at any time without interrupting normal execution. Changes to CKRL will take affect
on the next prescaler overflow. When CKRL is updated, the new frequency will take affect within
a maximum period of 1024 x t
CKRL6
TPS2
6
6
CKRL5
TPS1
5
5
f
SYS
CKRL4
AT89LP51RD2/ED2/ID2 Preliminary
TPS0
OSC
f
4
4
SYS
=
. The prescaler is disabled by reset.
OSC
---------------------------------------------- -
4
=
×
f
--------------------------- -
f
is the frequency of the selected clock source and X2 is the
(
OSC
OSC
255 CKRL
CKRL3
2
×
×
–
—
3
3
2
2
X2
X2
)
(
CKRL
CKRL2
(
—
CKRL 255
2
2
=
255
<
Reset Value = 0101 XXXXB
Reset Value = 1111 1111B
)
CKRL1
)
—
1
1
CKRL0
—
0
0
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