AT25DF081-SSHN-B Atmel, AT25DF081-SSHN-B Datasheet - Page 8

• Manufacturer Part Number: AT25DF081-SSHN-B
• Description: IC FLASH 8MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF081-SSHN-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 66MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 7ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.65V
• Operating Supply Voltage (max): 1.95V
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 8
• Architecture: Sectored
• Supply Voltage (max): 1.95 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Current: 12 mA
• Mounting Style: SMD/SMT
• Organization: 64 KB x 16
• Memory Configuration: 4096 Pages X 256 Bytes
• Clock Frequency: 66MHz
• Supply Voltage Range: 1.65V To 1.95V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. Read Commands
7.1
Figure 7-1.
Figure 7-2.
8
Read Array
AT25DF081
SCK
SO
CS
Read Array – 0Bh Opcode
Read Array – 03h Opcode
SI
SCK
SO
CS
SI
MSB
HIGH-IMPEDANCE
0
The Read Array command can be used to sequentially read a continuous stream of data from
the device by simply providing the SCK signal once the initial starting address has been speci-
fied. The device incorporates an internal address counter that automatically increments on every
clock cycle.
Two opcodes, 0Bh and 03h, can be used for the Read Array command. The use of each opcode
depends on the maximum SCK frequency that will be used to read data from the device. The
0Bh opcode can be used at any SCK frequency up to the maximum specified by f
opcode can be used for lower frequency read operations up to the maximum specified by f
To perform the Read Array operation, the CS pin must first be asserted and the appropriate
opcode (0Bh or 03h) must be clocked into the device. After the opcode has been clocked in, the
three address bytes must be clocked in to specify the starting address location of the first byte to
read within the memory array. If the 0Bh opcode is used, then one don’t care byte must also be
clocked in after the three address bytes.
After the three address bytes (and the one don’t care byte if using opcode 0Bh) have been
clocked in, additional clock cycles will result in serial data being output on the SO pin. The data
is always output with the MSB of a byte first. When the last byte (0FFFFFh) of the memory array
has been read, the device will continue reading back at the beginning of the array (000000h). No
delays will be incurred when wrapping around from the end of the array to the beginning of the
array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
0
0
1
0
2
OPCODE
0
3
MSB
HIGH-IMPEDANCE
1
0
4
0
0
0
5
1
1
0
6
2
OPCODE
1
0
7
3
MSB
A
0
8
4
A
0
9
5
ADDRESS BITS A23-A0
A
1
10 11
6
A
1
7
MSB
A
A
12
8
A
A
9
ADDRESS BITS A23-A0
A
10 11
A
A
29 30
A
12
A
A
A
31 32
MSB
X
X
A
33
29 30
DON'T CARE
X
A
34
X
A
35
31 32
MSB
X
D
36
X
D
37 38
33
DATA BYTE 1
X
D
34
D
X
39
35
MSB
D
D
36
40
D
D
41
37 38
DATA BYTE 1
D
D
42 43
D
D
39 40
MSB
D
D
44
D
D
45
D
46
D
47 48
MSB
D
D
3674E–DFLASH–8/08
SCK
. The 03h
RDLF
.