AT25DF081-SSHN-B Atmel, AT25DF081-SSHN-B Datasheet - Page 26

IC FLASH 8MBIT 66MHZ 8SOIC

AT25DF081-SSHN-B

Manufacturer Part Number
AT25DF081-SSHN-B
Description
IC FLASH 8MBIT 66MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT25DF081-SSHN-B

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
8M (4096 pages x 256 bytes)
Speed
66MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Cell Type
NOR
Density
8Mb
Access Time (max)
7ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
SOIC
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.65V
Operating Supply Voltage (max)
1.95V
Supply Current
12mA
Mounting
Surface Mount
Pin Count
8
Architecture
Sectored
Supply Voltage (max)
1.95 V
Supply Voltage (min)
1.65 V
Maximum Operating Current
12 mA
Mounting Style
SMD/SMT
Organization
64 KB x 16
Memory Configuration
4096 Pages X 256 Bytes
Clock Frequency
66MHz
Supply Voltage Range
1.65V To 1.95V
Memory Case Style
SOIC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT25DF081-SSHN-B
Manufacturer:
ATMEL
Quantity:
4 300
11.3
26
Resume from Deep Power-Down
AT25DF081
In order exit the Deep Power-Down mode and resume normal device operation, the Resume
from Deep Power-Down command must be issued. The Resume from Deep Power-Down com-
mand is the only command that the device will recognize while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of
ABh must be clocked into the device. Any additional data clocked into the device after the
opcode will be ignored. When the CS pin is deasserted, the device will exit the Deep Power-
Down mode within the maximum time of t
has returned to the standby mode, normal command operations such as Read Array can be
resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not
deasserted on an even byte boundary (multiples of eight bits), then the device will abort the
operation and return to the Deep Power-Down mode.
Figure 11-3. Resume from Deep Power-Down
SCK
SO
I
CS
CC
SI
Deep Power-Down Mode Current
HIGH-IMPEDANCE
MSB
1
0
Active Current
0
1
1
2
OPCODE
0
3
RDPD
1
4
0
5
and return to the standby mode. After the device
1
6
1
7
Standby Mode Current
t
RDPD
3674E–DFLASH–8/08

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