MT48H8M16LFB4-8 IT TR Micron Technology Inc, MT48H8M16LFB4-8 IT TR Datasheet - Page 12

• Manufacturer Part Number: MT48H8M16LFB4-8 IT TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1051-2

Figure 5: CAS Latency
Table 5:
Operating Mode
Write Burst Mode
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
CAS Latency
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 5 indicates the operating frequencies
at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
COMMAND
COMMAND
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-
grammed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and
WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
CLK
CLK
DQ
DQ
Speed
-10
-8
READ
READ
T0
T0
CL = 2
NOP
NOP
T1
T1
t
t AC
LZ
CL = 3
CAS Latency = 2
12
T2
NOP
T2
NOP
Allowable Operating Frequency (MHz)
≤ 83.3
t
t AC
≤ 104
LZ
D
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
128Mb: x16 Mobile SDRAM
T4
Mode Register Definition
©2003 Micron Technology, Inc. All rights reserved.
CAS Latency = 3
≤ 125
≤ 104