MT48H8M16LFB4-8 IT TR Micron Technology Inc, MT48H8M16LFB4-8 IT TR Datasheet - Page 22

• Manufacturer Part Number: MT48H8M16LFB4-8 IT TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1051-2

Figure 11: Random READ Accesses
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
Note:
COMMAND
COMMAND
The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13 on
page 23. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE
command (DQM latency is 2 clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQ will go High-Z (or remain High-
Z), regardless of the state of the DQM signal, provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in
on page
be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked.
page 23
avoided without adding a NOP cycle, and
additional NOP is needed. A fixed-length READ burst may be followed by, or truncated
with, a PRECHARGE command to the same bank (provided that auto precharge was not
activated), and a full-page burst may be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be issued x cycles before the clock edge
at which the last desired data element is valid, where x equals the CAS latency minus
one. This is shown in
+ 3 is either the last of a burst of four or the last desired of a longer burst. Following the
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
shows the case where the clock frequency allows for bus contention to be
24, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would
T0
BANK,
T0
BANK,
COL n
COL n
READ
READ
CL = 2
CL = 3
T1
T1
READ
BANK,
BANK,
COL a
READ
COL a
Figure 14 on page 24
T2
BANK,
T2
COL x
BANK,
READ
READ
COL x
22
D
OUT
n
T3
T3
TRANSITIONING DATA
BANK,
COL m
READ
READ
BANK,
COL m
D
D
OUT
a
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 13 on page 23
for each possible CAS latency; data element n
T4
T4
NOP
NOP
D
D
OUT
x
OUT
a
T5
T5
NOP
NOP
128Mb: x16 Mobile SDRAM
D
D
m
OUT
OUT
x
DON’T CARE
T6
NOP
D
OUT
m
©2003 Micron Technology, Inc. All rights reserved.
shows the case where the
Figure 13 on
Figure 14
READs