MT48H8M16LFB4-8 IT TR Micron Technology Inc, MT48H8M16LFB4-8 IT TR Datasheet - Page 7

• Manufacturer Part Number: MT48H8M16LFB4-8 IT TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1051-2

Table 3:
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
H7, H8, J8, J7, J3, J2, H3,
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
H2, H1, G3, H9, G2
54-BALL FBGA
A7, B3, C7, D3
A3, B7, C3, D7
C1, B2, B1, A2
A9, E7, J9
A1, E3, J1
F7, F8, F9
G7, G8
E2, G1
E8, F1
G9
F2
F3
Ball Descriptions
CAS#, RAS#,
DQ0–DQ15
SYMBOL
BA0, BA1
A0–A11
LDQM,
UDQM
V
V
WE#
CLK
CKE
V
CS#
V
NC
DD
SS
DD
SS
Q
Q
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Core Power Supply.
Supply Ground.
TYPE
Input
Input
Input
Input
Input
Input
Input
I/O
–
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank), DEEP POWER-DOWN (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. LDQM corresponds to
DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied. These balls also
select between the mode register and the extended mode register.
Address Inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
Data Input/Output: Data bus.
Internally Not Connected: These could be left unconnected, but it is
recommended they be connected or V
but may be used as A12 in future designs.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
128Mb: x16 Mobile SDRAM
SS
. G1 is a no connect for this part
General Description
©2003 Micron Technology, Inc. All rights reserved.