MT48H8M16LFB4-8 IT TR Micron Technology Inc, MT48H8M16LFB4-8 IT TR Datasheet - Page 16

• Manufacturer Part Number: MT48H8M16LFB4-8 IT TR
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M16LFB4-8 IT TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1051-2

COMMAND INHIBIT
NO OPERATION (NOP)
LOAD MODE REGISTER
ACTIVE
READ
WRITE
PRECHARGE
PDF: 09005aef80c97087/Source: 09005aef80c97015
MT48H8M16_2.fm - Rev. E 3/05 EN
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
The mode register is loaded via inputs A0–A11, BA0, BA1. See “Mode Register Defini-
tion” on page 8. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER
commands can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until
The values of the mode register and extended mode register will be retained even when
exiting deep power-down.
The ACTIVE command is used to open (or activate) a row in a particular bank for a sub-
sequent access. The value on the BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0–A11 selects the row. This row remains active (or open) for accesses
until a precharge command is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be pre-
charged at the end of the read burst; if auto precharge is not selected, the row will remain
open for subsequent accesses. Read data appears on the DQ subject to the logic level on
the DQM inputs 2 clocks earlier. If a given DQM signal was registered HIGH, the corre-
sponding DQ will be High-Z two clocks later; if the DQM signal was registered LOW, the
DQ will provide valid data.
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be pre-
charged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to mem-
ory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored,
and a write will not be executed to that byte/column location.
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
whether one or all banks are to be precharged, and in the case where only 1 bank is to be
t
RP) after the PRECHARGE command is issued. Input A10 determines
16
t
MRD is met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16 Mobile SDRAM
©2003 Micron Technology, Inc. All rights reserved.
Commands