APMOTOR56F8000E Freescale Semiconductor, APMOTOR56F8000E Datasheet - Page 66

• Manufacturer Part Number: APMOTOR56F8000E
• Description: KIT DEMO MOTOR CTRL SYSTEM
• Manufacturer: Freescale Semiconductor
• Type: Motor / Motion Controllers & Driversr

Specifications of APMOTOR56F8000E

• Accessory Type: Motor Controller
• Input Voltage: 9 V
• Interface Type: RS-232
• Product: Power Management Modules
• For Use With/related Products: DEMO56F8013, DEMO56F8013-E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.1.2
This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode.
6.3.1.3
This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode.
6.3.1.4
This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode.
6.3.1.5
This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in
LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is
in Sleep mode and using Stop mode to reduce power consumption.
6.3.1.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.1.7
This bit selects the input of Timer Channel 3 to be from the PWM sync signal or GPIO pin.
6.3.1.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.1.9
6.3.1.10
Writing 1 to this field will cause the part to reset.
66
•
•
•
•
•
•
•
•
•
•
•
•
•
1 = Timer Channel 3 enabled in Stop mode
0 = Timer Channel 2 disabled in Stop mode
1 = Timer Channel 2 enabled in Stop mode
0 = Timer Channel 1 disabled in Stop mode
1 = Timer Channel 1 enabled in Stop mode
0 = Timer Channel 0 disabled in Stop mode
1 = Timer Channel 0 enabled in Stop mode
0 = SCI disabled in Stop mode
1 = SCI enabled in Stop mode
1 = Timer Channel 3 Input from PWM sync signal
0 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Timer Channel 2 Stop Disable (TC2_SD)—Bit 14
Timer Channel 1 Stop Disable (TC1_SD)—Bit 13
Timer Channel 0 Stop Disable (TC0_SD)—Bit 12
SCI Stop Disable (SCI_SD)—Bit 11
Reserved—Bit 10
Timer Channel 3 Input (TC3_INP)—Bit 9
Reserved—Bits 8–6
OnCE Enable (ONCEEBL)—Bit 5
Software Reset (SWRST)—Bit 4
56F8014 Technical Data, Rev. 11
Freescale Semiconductor