APMOTOR56F8000E Freescale Semiconductor, APMOTOR56F8000E Datasheet - Page 80

KIT DEMO MOTOR CTRL SYSTEM

APMOTOR56F8000E

Manufacturer Part Number
APMOTOR56F8000E
Description
KIT DEMO MOTOR CTRL SYSTEM
Manufacturer
Freescale Semiconductor
Type
Motor / Motion Controllers & Driversr

Specifications of APMOTOR56F8000E

Accessory Type
Motor Controller
Input Voltage
9 V
Interface Type
RS-232
Product
Power Management Modules
For Use With/related Products
DEMO56F8013, DEMO56F8013-E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
POR resets are extended 64 MSTR_OSC clocks to stabilize the power supply. All resets are subsequently
extended for an additional 32 MSTR_OSC clocks and 64 system clocks as the various internal reset
controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a POR reset
from when power comes on to when code is running is 28μS. An external reset generation chip may also
be used. Resets may be asserted asynchronously, but they are always released internally on a rising edge
of the system clock.
80
RESET IN
Power-On
External
(active
(active
(active
Reset
COP
low)
low)
Figure 6-15 Sources of RESET Functional Diagram (Test modes not included)
low)
RESET
POR
Delay blocks assert immediately and
deassert only after the programmed
number of clock cycles.
pulse shaper
MSTR_OSC
Delay 64
Clocks
SW Reset
COMBINED_RST
pulse shaper
MSTR_OSC
Delay 32
Clocks
56F8014 Technical Data, Rev. 11
EXTENDED_POR
pulse shaper
CLKGEN_RST
sys clocks
Delay 32
pulse shaper
sys clocks
Delay 32
OCCS
PERIP_RST
CORE_RST
Freescale Semiconductor
Peripherals
Subsystem
Memory
JTAG
56800E

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