DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 109

• Manufacturer Part Number: DS26524DK
• Description: KIT DESIGN FOR DS26524
• Manufacturer: Maxim Integrated Products

Specifications of DS26524DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: DS26524
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Description:
Register Address:
Bit #
Name
Default
Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine the
configuration of the IBO (interleaved bus) multiplexer. These bits should be used in conjunction with the Rx and Tx
IBO control registers within each of the framer units. Additional information concerning the IBO multiplexer is given
in Section 8.8.2.
Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on
the BPCLK pin.
Bit 3: Receive Loss of Signal/Signaling Freeze Select (RLOSSFS). This bit controls the function of all four
AL/RSIGF/FLOS pins. The receive LOS is further selected between framer LOS and LIU LOS by GTCR2.2.
Bit 2: Receive Frame/Multiframe Sync Select (RFMSS). This bit controls the function of all four
RMSYNC/RFSYNC pins.
Bit 1: Transmit Channel Block/Clock Select (TCBCS). This bit controls the function of all four TCHBLK/CLK
pins.
Bit 0: Receive Channel Block/Clock Select (RCBCS). This bit controls the function of all four RCHBLK/CLK pins.
BPCLK1
IBOMS1
0
0
1
1
0
0
1
1
0 = AL/RSIGF/FLOS pin outputs RLOS[1:4] (receive loss)
1 = AL/RSIGF/FLOS pin outputs RSIGF[1:4] (receive-signaling freeze)
0 = RMSYNC/RFSYNC pin outputs RFSYNC[1:4] (receive frame sync)
1 = RMSYNC/RFSYNC pin outputs RMSYNC[1:4] (receive multiframe sync)
0 = TCHBLK/CLK pin outputs TCHBLK[1:4] (transmit channel block)
1 = TCHBLK/CLK pin outputs TCHCLK[1:4] (transmit channel clock)
0 = RCHBLK/CLK pin outputs RCHBLK[1:4] (receive channel block)
1 = RCHBLK/CLK pin outputs RCHCLK[1:4] (receive channel clock)
IBOMS1
7
0
BPCLK0
IBOMS0
0
1
0
1
0
1
0
1
IBOMS0
GFCR
Global Framer Control Register
0F1h
6
0
IBO multiplexer disabled
2 devices on bus (4.096MHz)
4 devices on bus (8.192MHz)
8 devices on bus (16.384MHz)
BPCLK FREQUENCY
BPCLK1
IBO MODE
16.384MHz
5
0
2.048MHz
4.096MHz
8.192MHz
BPCLK0
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4
0
RFLOSSFS
3
0
RFMSS
2
0
TCBCS
1
0
RCBCS
0
0